AES/MASKED Simulation Results

Wednesday October 02 2024 15:31:08 UTC

GitHub Revision: `1cb1c3d135`

Branch: os_regression_2024_10_02

Simulator: XCELIUM

Build randomization enabled with --build-seed 110153111371602750214979040795005912991145924440069071731765206333111748946968

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	63.837us	1	1	100.00
V1	smoke	aes_smoke	1.467m	202.070us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	5.000s	95.783us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	116.514us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	20.000s	2.939ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	193.434us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	218.928us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	116.514us	20	20	100.00
		aes_csr_aliasing	7.000s	193.434us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.467m	202.070us	50	50	100.00
		aes_config_error	1.767m	3.567ms	50	50	100.00
		aes_stress	1.317m	84.010us	50	50	100.00
V2	key_length	aes_smoke	1.467m	202.070us	50	50	100.00
		aes_config_error	1.767m	3.567ms	50	50	100.00
		aes_stress	1.317m	84.010us	50	50	100.00
V2	back2back	aes_stress	1.317m	84.010us	50	50	100.00
		aes_b2b	1.583m	677.400us	50	50	100.00
V2	backpressure	aes_stress	1.317m	84.010us	50	50	100.00
V2	multi_message	aes_smoke	1.467m	202.070us	50	50	100.00
		aes_config_error	1.767m	3.567ms	50	50	100.00
		aes_stress	1.317m	84.010us	50	50	100.00
		aes_alert_reset	1.433m	195.299us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.550m	60.779us	50	50	100.00
		aes_config_error	1.767m	3.567ms	50	50	100.00
		aes_alert_reset	1.433m	195.299us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.233m	62.677us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	168.342us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.433m	195.299us	50	50	100.00
V2	stress	aes_stress	1.317m	84.010us	50	50	100.00
V2	sideload	aes_stress	1.317m	84.010us	50	50	100.00
		aes_sideload	1.517m	331.754us	50	50	100.00
V2	deinitialization	aes_deinit	1.550m	80.923us	50	50	100.00
V2	stress_all	aes_stress_all	1.300m	9.425ms	10	10	100.00
V2	alert_test	aes_alert_test	1.183m	60.639us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	129.703us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	129.703us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	5.000s	95.783us	5	5	100.00
		aes_csr_rw	5.000s	116.514us	20	20	100.00
		aes_csr_aliasing	7.000s	193.434us	5	5	100.00
		aes_same_csr_outstanding	6.000s	287.601us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	5.000s	95.783us	5	5	100.00
		aes_csr_rw	5.000s	116.514us	20	20	100.00
		aes_csr_aliasing	7.000s	193.434us	5	5	100.00
		aes_same_csr_outstanding	6.000s	287.601us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.983m	4.403ms	50	50	100.00
V2S	fault_inject	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_cipher_fi	1.033m	59.407us	289	350	82.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	151.422us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	151.422us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	151.422us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	151.422us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	111.969us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	565.927us	5	5	100.00
		aes_tl_intg_err	10.000s	505.869us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	505.869us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.433m	195.299us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	151.422us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.467m	202.070us	50	50	100.00
		aes_stress	1.317m	84.010us	50	50	100.00
		aes_alert_reset	1.433m	195.299us	50	50	100.00
		aes_core_fi	2.300m	10.075ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	151.422us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.533m	84.256us	50	50	100.00
		aes_stress	1.317m	84.010us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.317m	84.010us	50	50	100.00
		aes_sideload	1.517m	331.754us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.533m	84.256us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.533m	84.256us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.533m	84.256us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.533m	84.256us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.533m	84.256us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.317m	84.010us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.317m	84.010us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.517m	89.623us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_cipher_fi	1.033m	59.407us	289	350	82.57
		aes_ctr_fi	56.000s	71.124us	48	50	96.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.517m	89.623us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_cipher_fi	1.033m	59.407us	289	350	82.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.033m	59.407us	289	350	82.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.517m	89.623us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_ctr_fi	56.000s	71.124us	48	50	96.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_cipher_fi	1.033m	59.407us	289	350	82.57
		aes_ctr_fi	56.000s	71.124us	48	50	96.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.433m	195.299us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_cipher_fi	1.033m	59.407us	289	350	82.57
		aes_ctr_fi	56.000s	71.124us	48	50	96.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_cipher_fi	1.033m	59.407us	289	350	82.57
		aes_ctr_fi	56.000s	71.124us	48	50	96.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_ctr_fi	56.000s	71.124us	48	50	96.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.517m	89.623us	49	50	98.00
		aes_control_fi	1.033m	46.460us	254	300	84.67
		aes_cipher_fi	1.033m	59.407us	289	350	82.57
V2S		TOTAL			874	985	88.73
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	40.000s	1.819ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1481	1602	92.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	98.57	96.37	99.45	95.78	97.72	100.00	98.96	98.00

Failure Buckets

Job timed out after * minutes has 95 failures:
- Test aes_control_fi has 40 failures.
  - 13.aes_control_fi.73819482632452932415062612833344526999559938308099747664503807352039131857458
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_control_fi.58625333205372553684750686654554899480982310123073508998380624388252798005747
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 38 more failures.
- Test aes_cipher_fi has 53 failures.
  - 13.aes_cipher_fi.43932925275347832410527986305341976523212607005259391134811082467325820894249
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 37.aes_cipher_fi.66180520369817370245181293285306829838579578966603998012981805354718934633573
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 51 more failures.
- Test aes_ctr_fi has 2 failures.
  - 13.aes_ctr_fi.87733698327856154665346854811260135582471538874528624416069521362155073036179
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/13.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 37.aes_ctr_fi.28378845044015622449754983073820393330970508827632045330963970125833901193230
    Log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/37.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 1.aes_cipher_fi.76996053576119211610809424790582524439129695620533211272703416452667312388033
    Line 139, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10054220793 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10054220793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.aes_cipher_fi.68265370205829797649667606555430788795799333090482165585235788522740135774929
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/96.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10048406782 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10048406782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 95.aes_control_fi.72193943519084731525926146686703547826661440946446569366624544706988991277490
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/95.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016094671 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016094671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 96.aes_control_fi.94557480285607900530965631020233166682062225392654687325835921226354602981403
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/96.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008252873 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008252873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.24654801999236905377399327123856363378341877420726975298837543137598654959369
Line 126, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  23769149 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  23769149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.6587989576554528931413060973186505448039906900044844852656524610426804125342
Line 140, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @   8110684 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   8110684 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

6.aes_stress_all_with_rand_reset.17220033530864894310961978449674635772739611593653794444924995361772308208732
Line 217, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1818663419 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1818663419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.27651991509938582141367855250832447144160407939180307576553544604421724719554
Line 888, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2207389768 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2207389768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.10217999132256750151010622042559346029295522228078337293619765818173676016082
    Line 244, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 841397113 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 841397113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

22.aes_fi.15952371499731297753163933099949736889618960936065667854264671036263288021504
Line 1295, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/22.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 15972921 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 15931254 PS)
  UVM_ERROR @  15972921 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  15972921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 64.aes_core_fi.66536283988219531173477360646226482757789948685291431025804631069815658926101
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_02/aes_masked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10075313269 ps: (csr_utils_pkg.sv:611) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1214d284, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10075313269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```