AES/MASKED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: XCELIUM

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	14.000s	84.249us	1	1	100.00
V1	smoke	aes_smoke	1.800m	182.734us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	32.000s	76.336us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.950m	92.088us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	35.000s	536.349us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	31.000s	183.609us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.533m	263.345us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.950m	92.088us	20	20	100.00
		aes_csr_aliasing	31.000s	183.609us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.800m	182.734us	50	50	100.00
		aes_config_error	1.717m	129.076us	50	50	100.00
		aes_stress	1.917m	647.419us	50	50	100.00
V2	key_length	aes_smoke	1.800m	182.734us	50	50	100.00
		aes_config_error	1.717m	129.076us	50	50	100.00
		aes_stress	1.917m	647.419us	50	50	100.00
V2	back2back	aes_stress	1.917m	647.419us	50	50	100.00
		aes_b2b	2.333m	682.876us	50	50	100.00
V2	backpressure	aes_stress	1.917m	647.419us	50	50	100.00
V2	multi_message	aes_smoke	1.800m	182.734us	50	50	100.00
		aes_config_error	1.717m	129.076us	50	50	100.00
		aes_stress	1.917m	647.419us	50	50	100.00
		aes_alert_reset	1.867m	87.098us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.583m	53.004us	50	50	100.00
		aes_config_error	1.717m	129.076us	50	50	100.00
		aes_alert_reset	1.867m	87.098us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.033m	2.266ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	22.000s	337.218us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.867m	87.098us	50	50	100.00
V2	stress	aes_stress	1.917m	647.419us	50	50	100.00
V2	sideload	aes_stress	1.917m	647.419us	50	50	100.00
		aes_sideload	1.833m	85.434us	50	50	100.00
V2	deinitialization	aes_deinit	1.700m	298.699us	50	50	100.00
V2	stress_all	aes_stress_all	1.083m	2.479ms	10	10	100.00
V2	alert_test	aes_alert_test	1.667m	92.886us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.467m	258.263us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.467m	258.263us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	32.000s	76.336us	5	5	100.00
		aes_csr_rw	1.950m	92.088us	20	20	100.00
		aes_csr_aliasing	31.000s	183.609us	5	5	100.00
		aes_same_csr_outstanding	1.900m	90.982us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	32.000s	76.336us	5	5	100.00
		aes_csr_rw	1.950m	92.088us	20	20	100.00
		aes_csr_aliasing	31.000s	183.609us	5	5	100.00
		aes_same_csr_outstanding	1.900m	90.982us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	2.233m	3.111ms	50	50	100.00
V2S	fault_inject	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_cipher_fi	1.017m	64.915us	280	350	80.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.983m	200.868us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.983m	200.868us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.983m	200.868us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.983m	200.868us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.717m	135.032us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	24.000s	916.295us	5	5	100.00
		aes_tl_intg_err	2.067m	123.132us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.067m	123.132us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.867m	87.098us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.983m	200.868us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.800m	182.734us	50	50	100.00
		aes_stress	1.917m	647.419us	50	50	100.00
		aes_alert_reset	1.867m	87.098us	50	50	100.00
		aes_core_fi	1.867m	703.619us	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.983m	200.868us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.683m	50.901us	50	50	100.00
		aes_stress	1.917m	647.419us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.917m	647.419us	50	50	100.00
		aes_sideload	1.833m	85.434us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.683m	50.901us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.683m	50.901us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.683m	50.901us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.683m	50.901us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.683m	50.901us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.917m	647.419us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.917m	647.419us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.867m	82.681us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_cipher_fi	1.017m	64.915us	280	350	80.00
		aes_ctr_fi	59.000s	79.464us	42	50	84.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.867m	82.681us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_cipher_fi	1.017m	64.915us	280	350	80.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	64.915us	280	350	80.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.867m	82.681us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_ctr_fi	59.000s	79.464us	42	50	84.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_cipher_fi	1.017m	64.915us	280	350	80.00
		aes_ctr_fi	59.000s	79.464us	42	50	84.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.867m	87.098us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_cipher_fi	1.017m	64.915us	280	350	80.00
		aes_ctr_fi	59.000s	79.464us	42	50	84.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_cipher_fi	1.017m	64.915us	280	350	80.00
		aes_ctr_fi	59.000s	79.464us	42	50	84.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_ctr_fi	59.000s	79.464us	42	50	84.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.867m	82.681us	49	50	98.00
		aes_control_fi	1.000m	84.763us	231	300	77.00
		aes_cipher_fi	1.017m	64.915us	280	350	80.00
V2S		TOTAL			836	985	84.87
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.117m	715.579us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1443	1602	90.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.31	98.50	96.19	99.43	95.67	97.64	97.78	99.11	96.41

Failure Buckets

Job timed out after * minutes has 137 failures:
- Test aes_control_fi has 65 failures.
  - 13.aes_control_fi.105274267513174215279718698692335037677058572446377842078461096760100843071093
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_control_fi.77723190790919555473056979096511463489948945060878755078855371613042920771792
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 63 more failures.
- Test aes_cipher_fi has 64 failures.
  - 13.aes_cipher_fi.17120285926241837456920955426620625047666442345535703646301119105543363645684
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_cipher_fi.92102357278848086269010157013387261823157172694210219600176119787384276732758
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 62 more failures.
- Test aes_ctr_fi has 8 failures.
  - 13.aes_ctr_fi.4603770347744080007863865208078956461257432958506719881260360314275376054584
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/13.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_ctr_fi.12144600916799549787567703582474056774340725791345814521119313274772928831965
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/14.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.104501047044622791999468177825680274228212112213050087083635381176079552292075
Line 798, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 598030003 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 598030003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.21242635350811612665250433453455143527289245140123137769964997000603343082826
Line 981, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 715579396 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 715579396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 33.aes_cipher_fi.47194900825346393211918644185125652019814439396939247277895027903949947336658
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013505428 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013505428 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 107.aes_cipher_fi.64720245377179073131500109130616619330866898923135866249411083511885992591522
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/107.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10109743554 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10109743554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 0.aes_control_fi.2425546085836317185261838308300657350679188078197448642460481488477624569162
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008807341 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008807341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 107.aes_control_fi.114862240603882716015425082898621612702741257180738504408852158953305547492166
    Line 125, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/107.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020363525 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020363525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.16717623116460683976151458404960489960875498676977983956449116054041596769956
    Line 168, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 234964370 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 234964370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.107728861963877480259336855706258541760325520832469456133444332468979100600005
    Line 157, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 257729786 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 257729786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_cipher_core.sv,865): Assertion AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (* cycles, starting * PS) has 1 failures:

Test aes_core_fi has 1 failures.

35.aes_core_fi.85662472956130140972144028307472131086858399764329474846362711394244089907220
Line 131, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/35.aes_core_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_cipher_core.sv,865): (time 9771484 PS) Assertion tb.dut.u_aes_core.u_aes_cipher_core.gen_sec_cm_key_masking_svas.AesSecCmKeyMaskingInitialPrngUpdateKeyExpand has failed (2 cycles, starting 9761067 PS)
  UVM_ERROR @   9771484 ps: (aes_cipher_core.sv:865) [ASSERT FAILED] AesSecCmKeyMaskingInitialPrngUpdateKeyExpand
  UVM_INFO @   9771484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 39.aes_fi.111769217920206519693934472056638158329678516150214338405981547351383364177423
    Line 7811, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_masked-sim-xcelium/39.aes_fi/latest/run.log
```
  UVM_FATAL @  19056854 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  19056854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```