AES/MASKED Simulation Results

Wednesday October 09 2024 01:12:40 UTC

GitHub Revision: `29d22a60a2`

Branch: os_regression_2024_10_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 53714374671147886608112573291731904665579606104149618024735414983036052389689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	117.880us	1	1	100.00
V1	smoke	aes_smoke	1.767m	799.450us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	134.813us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.533m	62.991us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	3.040ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	284.635us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.900m	75.972us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.533m	62.991us	20	20	100.00
		aes_csr_aliasing	5.000s	284.635us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.767m	799.450us	50	50	100.00
		aes_config_error	1.633m	239.914us	50	50	100.00
		aes_stress	1.850m	2.160ms	50	50	100.00
V2	key_length	aes_smoke	1.767m	799.450us	50	50	100.00
		aes_config_error	1.633m	239.914us	50	50	100.00
		aes_stress	1.850m	2.160ms	50	50	100.00
V2	back2back	aes_stress	1.850m	2.160ms	50	50	100.00
		aes_b2b	1.900m	253.836us	50	50	100.00
V2	backpressure	aes_stress	1.850m	2.160ms	50	50	100.00
V2	multi_message	aes_smoke	1.767m	799.450us	50	50	100.00
		aes_config_error	1.633m	239.914us	50	50	100.00
		aes_stress	1.850m	2.160ms	50	50	100.00
		aes_alert_reset	1.683m	111.666us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.767m	93.334us	50	50	100.00
		aes_config_error	1.633m	239.914us	50	50	100.00
		aes_alert_reset	1.683m	111.666us	50	50	100.00
V2	trigger_clear_test	aes_clear	3.117m	3.508ms	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	1.393ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.683m	111.666us	50	50	100.00
V2	stress	aes_stress	1.850m	2.160ms	50	50	100.00
V2	sideload	aes_stress	1.850m	2.160ms	50	50	100.00
		aes_sideload	1.683m	77.076us	50	50	100.00
V2	deinitialization	aes_deinit	1.833m	1.432ms	50	50	100.00
V2	stress_all	aes_stress_all	2.667m	1.089ms	10	10	100.00
V2	alert_test	aes_alert_test	1.567m	57.184us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.933m	94.617us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.933m	94.617us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	134.813us	5	5	100.00
		aes_csr_rw	1.533m	62.991us	20	20	100.00
		aes_csr_aliasing	5.000s	284.635us	5	5	100.00
		aes_same_csr_outstanding	1.917m	68.012us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	134.813us	5	5	100.00
		aes_csr_rw	1.533m	62.991us	20	20	100.00
		aes_csr_aliasing	5.000s	284.635us	5	5	100.00
		aes_same_csr_outstanding	1.917m	68.012us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.750m	197.992us	50	50	100.00
V2S	fault_inject	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_cipher_fi	1.017m	92.765us	294	350	84.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.917m	58.114us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.917m	58.114us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.917m	58.114us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.917m	58.114us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.917m	372.104us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.717m	1.687ms	5	5	100.00
		aes_tl_intg_err	1.933m	711.746us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.933m	711.746us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.683m	111.666us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.917m	58.114us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.767m	799.450us	50	50	100.00
		aes_stress	1.850m	2.160ms	50	50	100.00
		aes_alert_reset	1.683m	111.666us	50	50	100.00
		aes_core_fi	1.833m	59.277us	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.917m	58.114us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.750m	75.594us	50	50	100.00
		aes_stress	1.850m	2.160ms	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.850m	2.160ms	50	50	100.00
		aes_sideload	1.683m	77.076us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.750m	75.594us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.750m	75.594us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.750m	75.594us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.750m	75.594us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.750m	75.594us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.850m	2.160ms	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.850m	2.160ms	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.700m	166.639us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_cipher_fi	1.017m	92.765us	294	350	84.00
		aes_ctr_fi	56.000s	81.237us	40	50	80.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.700m	166.639us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_cipher_fi	1.017m	92.765us	294	350	84.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	92.765us	294	350	84.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.700m	166.639us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_ctr_fi	56.000s	81.237us	40	50	80.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_cipher_fi	1.017m	92.765us	294	350	84.00
		aes_ctr_fi	56.000s	81.237us	40	50	80.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.683m	111.666us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_cipher_fi	1.017m	92.765us	294	350	84.00
		aes_ctr_fi	56.000s	81.237us	40	50	80.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_cipher_fi	1.017m	92.765us	294	350	84.00
		aes_ctr_fi	56.000s	81.237us	40	50	80.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_ctr_fi	56.000s	81.237us	40	50	80.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.700m	166.639us	50	50	100.00
		aes_control_fi	1.033m	241.215us	250	300	83.33
		aes_cipher_fi	1.017m	92.765us	294	350	84.00
V2S		TOTAL			864	985	87.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.300m	1.550ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1471	1602	91.82

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.54	96.30	99.42	95.78	97.64	97.78	98.96	97.80

Failure Buckets

Job timed out after * minutes has 98 failures:
- Test aes_control_fi has 44 failures.
  - 4.aes_control_fi.14741195385018361098388524069527921536993137072005485191406179457525400331769
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 5.aes_control_fi.69767041584604517101792341270457736316963367040378486062615206808245645721250
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 42 more failures.
- Test aes_cipher_fi has 44 failures.
  - 4.aes_cipher_fi.25361347832967892070570100539821884762254645806280825647213647132044411280557
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 5.aes_cipher_fi.46065949320805145458639773031651642672540992464516808762229672920578720977290
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 42 more failures.
- Test aes_ctr_fi has 10 failures.
  - 4.aes_ctr_fi.66078066095285519673211729473793196823970871091348195399695005886948677029941
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/4.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 5.aes_ctr_fi.105625813061592812282082464699459895849546109390663518957645334133547380609158
    Log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/5.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 35.aes_cipher_fi.5204662369772954627166712070878726580213550305635987125568374150913673182578
    Line 141, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/35.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006320066 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006320066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.aes_cipher_fi.98257065547176634639230914240158273341890994836361822840399961271682089283840
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009780110 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009780110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.71822753254692006029959888715712902995005066331960584613138905990299757804876
Line 559, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 925273096 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 925273096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.11733929746317846306736134242235573510178771989524121227399098317471405274985
Line 843, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4723141361 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4723141361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 38.aes_control_fi.70506581827042271919429025022623943297390418771950094410831325056898721291829
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009620546 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009620546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 77.aes_control_fi.72187814152759868434894748603979260356332177667881126845889085870101564035371
    Line 142, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/77.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012382547 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012382547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 3.aes_core_fi.13162093413592960837731339738784073490692220105128797775642577238744699336670
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004260127 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004260127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_core_fi.113378093217900239013337124323491317770975524163916054066549771902967366782435
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007200040 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007200040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.23349053839218100664105913125762540424853999532033851140542868644047595631186
    Line 156, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  84254131 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  84254131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_stress_all_with_rand_reset.73107145352055576209143142025518251911906749775766540138447264995577443467688
    Line 160, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 199670461 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 199670461 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.114801426168729472960670141663948022840337645439683465777362036233823469634148
    Line 1002, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1549926429 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1549926429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.aes_stress_all_with_rand_reset.79075479809697299348315635458248788226888778685476851691483957345246817134537
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_10_08/aes_masked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 415296083 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 415296083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```