AES/MASKED Simulation Results

Friday October 11 2024 20:19:09 UTC

GitHub Revision: `8a1401d614`

Branch: os_regression_2024_10_11

Simulator: XCELIUM

Build randomization enabled with --build-seed 53663846044628477120113920685171085698887397097422685916033931805982305505364

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	87.585us	1	1	100.00
V1	smoke	aes_smoke	1.150m	266.550us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.250m	60.163us	5	5	100.00
V1	csr_rw	aes_csr_rw	2.050m	98.041us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	54.000s	2.052ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.250m	777.972us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	2.067m	152.566us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	2.050m	98.041us	20	20	100.00
		aes_csr_aliasing	1.250m	777.972us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.150m	266.550us	50	50	100.00
		aes_config_error	1.483m	269.842us	50	50	100.00
		aes_stress	1.567m	223.102us	50	50	100.00
V2	key_length	aes_smoke	1.150m	266.550us	50	50	100.00
		aes_config_error	1.483m	269.842us	50	50	100.00
		aes_stress	1.567m	223.102us	50	50	100.00
V2	back2back	aes_stress	1.567m	223.102us	50	50	100.00
		aes_b2b	1.467m	636.033us	50	50	100.00
V2	backpressure	aes_stress	1.567m	223.102us	50	50	100.00
V2	multi_message	aes_smoke	1.150m	266.550us	50	50	100.00
		aes_config_error	1.483m	269.842us	50	50	100.00
		aes_stress	1.567m	223.102us	50	50	100.00
		aes_alert_reset	1.200m	129.470us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.417m	61.732us	50	50	100.00
		aes_config_error	1.483m	269.842us	50	50	100.00
		aes_alert_reset	1.200m	129.470us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.433m	610.124us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	20.000s	388.140us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.200m	129.470us	50	50	100.00
V2	stress	aes_stress	1.567m	223.102us	50	50	100.00
V2	sideload	aes_stress	1.567m	223.102us	50	50	100.00
		aes_sideload	1.300m	109.112us	50	50	100.00
V2	deinitialization	aes_deinit	1.433m	850.577us	50	50	100.00
V2	stress_all	aes_stress_all	6.183m	58.369ms	10	10	100.00
V2	alert_test	aes_alert_test	58.000s	127.998us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	2.050m	386.442us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	2.050m	386.442us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.250m	60.163us	5	5	100.00
		aes_csr_rw	2.050m	98.041us	20	20	100.00
		aes_csr_aliasing	1.250m	777.972us	5	5	100.00
		aes_same_csr_outstanding	1.133m	94.307us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.250m	60.163us	5	5	100.00
		aes_csr_rw	2.050m	98.041us	20	20	100.00
		aes_csr_aliasing	1.250m	777.972us	5	5	100.00
		aes_same_csr_outstanding	1.133m	94.307us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.800m	3.302ms	50	50	100.00
V2S	fault_inject	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_cipher_fi	1.033m	48.004us	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.533m	121.493us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.533m	121.493us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.533m	121.493us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.533m	121.493us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.267m	219.109us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	28.000s	818.417us	5	5	100.00
		aes_tl_intg_err	1.917m	266.520us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.917m	266.520us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.200m	129.470us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.533m	121.493us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.150m	266.550us	50	50	100.00
		aes_stress	1.567m	223.102us	50	50	100.00
		aes_alert_reset	1.200m	129.470us	50	50	100.00
		aes_core_fi	2.083m	10.010ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.533m	121.493us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.267m	64.215us	50	50	100.00
		aes_stress	1.567m	223.102us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.567m	223.102us	50	50	100.00
		aes_sideload	1.300m	109.112us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.267m	64.215us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.267m	64.215us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.267m	64.215us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.267m	64.215us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.267m	64.215us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.567m	223.102us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.567m	223.102us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.617m	212.226us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_cipher_fi	1.033m	48.004us	319	350	91.14
		aes_ctr_fi	58.000s	57.712us	48	50	96.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.617m	212.226us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_cipher_fi	1.033m	48.004us	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.033m	48.004us	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.617m	212.226us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_ctr_fi	58.000s	57.712us	48	50	96.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_cipher_fi	1.033m	48.004us	319	350	91.14
		aes_ctr_fi	58.000s	57.712us	48	50	96.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.200m	129.470us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_cipher_fi	1.033m	48.004us	319	350	91.14
		aes_ctr_fi	58.000s	57.712us	48	50	96.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_cipher_fi	1.033m	48.004us	319	350	91.14
		aes_ctr_fi	58.000s	57.712us	48	50	96.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_ctr_fi	58.000s	57.712us	48	50	96.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.617m	212.226us	49	50	98.00
		aes_control_fi	1.017m	52.038us	257	300	85.67
		aes_cipher_fi	1.033m	48.004us	319	350	91.14
V2S		TOTAL			905	985	91.88
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.367m	1.131ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1512	1602	94.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.39	98.57	96.37	99.45	95.85	97.64	100.00	98.96	97.60

Failure Buckets

Job timed out after * minutes has 73 failures:
- Test aes_control_fi has 41 failures.
  - 5.aes_control_fi.60052019258858332896844611475312119085767692476230146044882520850836794033341
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 8.aes_control_fi.71339919717421429776170921745188614112461406786612636589034503366584891026433
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 39 more failures.
- Test aes_ctr_fi has 2 failures.
  - 20.aes_ctr_fi.63841866053754976459131459194614025530523234585980515721691465346303617585154
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/20.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 47.aes_ctr_fi.94661687823329291351239571849509973229582198246302903398017634498880494250965
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/47.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
- Test aes_cipher_fi has 30 failures.
  - 47.aes_cipher_fi.2083458752483092391982488809866798728011423376092583121858160802641518725005
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 49.aes_cipher_fi.74596997615356340568322432920705049236497940803985949414038207852681611237854
    Log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 28 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.48988814569510429735994574892314869702409914667270087155373836405147949737037
Line 297, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 379536028 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 379536028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.105594323264538730893164069689245597929288807058996799134425116234248885685807
Line 599, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2112340462 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2112340462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 16.aes_core_fi.63738527252835172764564994976595977539812183575726727178974397065578073994069
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/16.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009624695 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009624695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.aes_core_fi.6059936172351353336527317823134481006101556144317453734190372813532253881368
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007100125 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007100125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 3.aes_stress_all_with_rand_reset.47643886550066797739106124108546040753982156748141682639210829651539619976809
    Line 403, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 931695990 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 931695990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.62929794935953124861409500255020922627361332431336782224623035937806682560767
    Line 236, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 512577682 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 512577682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 150.aes_control_fi.92575952922027144317019019483949403897719271952922595409721474380502536415818
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/150.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10033522672 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033522672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 173.aes_control_fi.90876460985023403102883082262462862251879584843822564239351501818633195012615
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/173.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10028696216 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10028696216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.110814954146476401489228853001156760971485851254598321225249036152764685061791
    Line 159, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 950718852 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 950718852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 3.aes_fi.67655411387311677780552236755521628087296176810022799718591482240647992225114
    Line 19304, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/3.aes_fi/latest/run.log
```
  UVM_FATAL @  44522368 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  44522368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.4572672491410787900386211323288156975146455355616061992795326372517724113988
    Line 341, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 278326995 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 278326995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.43332659753860557424918389587740780109721559900443313297362372781533003405203
    Line 296, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 615897009 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 615897009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 43.aes_cipher_fi.81737169757377201564327004704858994498689073944828930466952017414838002031168
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_10_11/aes_masked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009567818 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009567818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```