AES/MASKED Simulation Results

Tuesday September 24 2024 01:05:57 UTC

GitHub Revision: `78ad89d1aa`

Branch: os_regression_2024_09_23

Simulator: XCELIUM

Build randomization enabled with --build-seed 34048022127553017884926631616394166155118623175048314192737094530054579848544

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	83.848us	1	1	100.00
V1	smoke	aes_smoke	1.900m	72.514us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	56.228us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	99.232us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	15.000s	1.149ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	131.536us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	548.751us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	99.232us	20	20	100.00
		aes_csr_aliasing	6.000s	131.536us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.900m	72.514us	50	50	100.00
		aes_config_error	1.967m	212.822us	50	50	100.00
		aes_stress	1.400m	140.657us	50	50	100.00
V2	key_length	aes_smoke	1.900m	72.514us	50	50	100.00
		aes_config_error	1.967m	212.822us	50	50	100.00
		aes_stress	1.400m	140.657us	50	50	100.00
V2	back2back	aes_stress	1.400m	140.657us	50	50	100.00
		aes_b2b	1.733m	706.549us	50	50	100.00
V2	backpressure	aes_stress	1.400m	140.657us	50	50	100.00
V2	multi_message	aes_smoke	1.900m	72.514us	50	50	100.00
		aes_config_error	1.967m	212.822us	50	50	100.00
		aes_stress	1.400m	140.657us	50	50	100.00
		aes_alert_reset	1.500m	1.488ms	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.950m	119.673us	50	50	100.00
		aes_config_error	1.967m	212.822us	50	50	100.00
		aes_alert_reset	1.500m	1.488ms	50	50	100.00
V2	trigger_clear_test	aes_clear	1.567m	175.400us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	12.000s	561.974us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.500m	1.488ms	50	50	100.00
V2	stress	aes_stress	1.400m	140.657us	50	50	100.00
V2	sideload	aes_stress	1.400m	140.657us	50	50	100.00
		aes_sideload	1.667m	91.726us	50	50	100.00
V2	deinitialization	aes_deinit	2.050m	76.484us	50	50	100.00
V2	stress_all	aes_stress_all	3.867m	2.868ms	9	10	90.00
V2	alert_test	aes_alert_test	1.433m	71.209us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	230.799us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	230.799us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	56.228us	5	5	100.00
		aes_csr_rw	5.000s	99.232us	20	20	100.00
		aes_csr_aliasing	6.000s	131.536us	5	5	100.00
		aes_same_csr_outstanding	5.000s	175.341us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	56.228us	5	5	100.00
		aes_csr_rw	5.000s	99.232us	20	20	100.00
		aes_csr_aliasing	6.000s	131.536us	5	5	100.00
		aes_same_csr_outstanding	5.000s	175.341us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	5.333m	8.914ms	50	50	100.00
V2S	fault_inject	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_cipher_fi	1.017m	89.810us	295	350	84.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	100.828us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	100.828us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	100.828us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	100.828us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	112.161us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	58.000s	691.810us	5	5	100.00
		aes_tl_intg_err	8.000s	326.872us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	326.872us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.500m	1.488ms	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	100.828us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.900m	72.514us	50	50	100.00
		aes_stress	1.400m	140.657us	50	50	100.00
		aes_alert_reset	1.500m	1.488ms	50	50	100.00
		aes_core_fi	1.383m	135.869us	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	100.828us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.083m	64.355us	50	50	100.00
		aes_stress	1.400m	140.657us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.400m	140.657us	50	50	100.00
		aes_sideload	1.667m	91.726us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.083m	64.355us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.083m	64.355us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.083m	64.355us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.083m	64.355us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.083m	64.355us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.400m	140.657us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.400m	140.657us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.000m	941.409us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_cipher_fi	1.017m	89.810us	295	350	84.29
		aes_ctr_fi	57.000s	87.183us	44	50	88.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.000m	941.409us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_cipher_fi	1.017m	89.810us	295	350	84.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	89.810us	295	350	84.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.000m	941.409us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_ctr_fi	57.000s	87.183us	44	50	88.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_cipher_fi	1.017m	89.810us	295	350	84.29
		aes_ctr_fi	57.000s	87.183us	44	50	88.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.500m	1.488ms	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_cipher_fi	1.017m	89.810us	295	350	84.29
		aes_ctr_fi	57.000s	87.183us	44	50	88.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_cipher_fi	1.017m	89.810us	295	350	84.29
		aes_ctr_fi	57.000s	87.183us	44	50	88.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_ctr_fi	57.000s	87.183us	44	50	88.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.000m	941.409us	50	50	100.00
		aes_control_fi	1.000m	56.817us	236	300	78.67
		aes_cipher_fi	1.017m	89.810us	295	350	84.29
V2S		TOTAL			858	985	87.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.433m	1.130ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1464	1602	91.39

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.27	98.47	96.12	99.38	95.63	97.72	97.78	99.11	96.61

Failure Buckets

Job timed out after * minutes has 118 failures:
- Test aes_ctr_fi has 6 failures.
  - 4.aes_ctr_fi.95683168104239858073113264354674367288983389694053201293960704701658258454214
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/4.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 17.aes_ctr_fi.86758749233098683048506089215061032293791027440207849512808540571489194735560
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/17.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 4 more failures.
- Test aes_control_fi has 60 failures.
  - 16.aes_control_fi.62747293166717084942406275390298953413585661491364698072958425215900753862453
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 43.aes_control_fi.20999060547410832742950956468882498175015441003974462468145312024416325939431
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 58 more failures.
- Test aes_cipher_fi has 52 failures.
  - 16.aes_cipher_fi.61396525206131923897144201125867838587149532814339400693448600311699840510697
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 17.aes_cipher_fi.27991779107339583456438129514757644093963636471262103774121622359432060793138
    Log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 50 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.97693441456458033085726360828239628320944715057791112717621862555795883974816
Line 159, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 159902486 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 159902486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.88520317451542498403963198536196684104171200551406842312527223947118155328494
Line 399, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 899307764 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 899307764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 27.aes_control_fi.14106364561880463908407150017105567361038256086502213221669619004212062525753
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10045658332 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10045658332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 46.aes_control_fi.54464346148319835013232406050024604617349995534851547009460656472498176274841
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10088344374 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10088344374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 46.aes_cipher_fi.107236335821023488819009596489103180842485947042777765429957159232473510435121
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10039412916 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10039412916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_cipher_fi.110271948342934833466568456727774963281958561154805213964061244267392643919206
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020734510 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020734510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 3.aes_core_fi.54899375069164181472257738955072349232887912635911366901903457291597816172625
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007423272 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007423272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.aes_core_fi.87510245028393649373577098454323091806372990872875824847777370919989477800958
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020026545 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020026545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.103764659037356378357879261594065453987648204263130492850699178852681067481725
    Line 407, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1358863795 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1358863795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:557) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 5.aes_stress_all.53416416995250771391150738462577078949636161260777898721837608138858799127164
    Line 12556, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/5.aes_stress_all/latest/run.log
```
  UVM_ERROR @ 165311755 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 165311755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.50175958692845057718387788623614911541117334089846712375323064422746524630337
    Line 259, in log /workspaces/repo/scratch/os_regression_2024_09_23/aes_masked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1559309117 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1559309117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```