AES/MASKED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: XCELIUM

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	104.232us	1	1	100.00
V1	smoke	aes_smoke	1.733m	188.787us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.250m	80.794us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.000m	57.121us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	58.000s	325.083us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	59.000s	446.189us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	57.000s	80.366us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.000m	57.121us	20	20	100.00
		aes_csr_aliasing	59.000s	446.189us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.733m	188.787us	50	50	100.00
		aes_config_error	1.417m	103.830us	50	50	100.00
		aes_stress	1.717m	70.135us	50	50	100.00
V2	key_length	aes_smoke	1.733m	188.787us	50	50	100.00
		aes_config_error	1.417m	103.830us	50	50	100.00
		aes_stress	1.717m	70.135us	50	50	100.00
V2	back2back	aes_stress	1.717m	70.135us	50	50	100.00
		aes_b2b	1.717m	270.170us	50	50	100.00
V2	backpressure	aes_stress	1.717m	70.135us	50	50	100.00
V2	multi_message	aes_smoke	1.733m	188.787us	50	50	100.00
		aes_config_error	1.417m	103.830us	50	50	100.00
		aes_stress	1.717m	70.135us	50	50	100.00
		aes_alert_reset	2.667m	298.276us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.867m	100.565us	50	50	100.00
		aes_config_error	1.417m	103.830us	50	50	100.00
		aes_alert_reset	2.667m	298.276us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.533m	107.139us	49	50	98.00
V2	nist_test_vectors	aes_nist_vectors	24.000s	363.573us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.667m	298.276us	50	50	100.00
V2	stress	aes_stress	1.717m	70.135us	50	50	100.00
V2	sideload	aes_stress	1.717m	70.135us	50	50	100.00
		aes_sideload	1.433m	70.893us	50	50	100.00
V2	deinitialization	aes_deinit	1.550m	137.544us	50	50	100.00
V2	stress_all	aes_stress_all	1.183m	3.408ms	10	10	100.00
V2	alert_test	aes_alert_test	2.483m	84.573us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	59.000s	92.158us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	59.000s	92.158us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.250m	80.794us	5	5	100.00
		aes_csr_rw	1.000m	57.121us	20	20	100.00
		aes_csr_aliasing	59.000s	446.189us	5	5	100.00
		aes_same_csr_outstanding	1.417m	89.796us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.250m	80.794us	5	5	100.00
		aes_csr_rw	1.000m	57.121us	20	20	100.00
		aes_csr_aliasing	59.000s	446.189us	5	5	100.00
		aes_same_csr_outstanding	1.417m	89.796us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.450m	178.140us	50	50	100.00
V2S	fault_inject	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_cipher_fi	1.000m	49.563us	280	350	80.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.167m	72.836us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.167m	72.836us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.167m	72.836us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.167m	72.836us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.000m	73.183us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	20.000s	6.008ms	5	5	100.00
		aes_tl_intg_err	59.000s	304.909us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	59.000s	304.909us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.667m	298.276us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.167m	72.836us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.733m	188.787us	50	50	100.00
		aes_stress	1.717m	70.135us	50	50	100.00
		aes_alert_reset	2.667m	298.276us	50	50	100.00
		aes_core_fi	1.533m	10.022ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.167m	72.836us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.600m	78.799us	50	50	100.00
		aes_stress	1.717m	70.135us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.717m	70.135us	50	50	100.00
		aes_sideload	1.433m	70.893us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.600m	78.799us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.600m	78.799us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.600m	78.799us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.600m	78.799us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.600m	78.799us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.717m	70.135us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.717m	70.135us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.883m	2.303ms	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_cipher_fi	1.000m	49.563us	280	350	80.00
		aes_ctr_fi	1.000m	94.415us	44	50	88.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.883m	2.303ms	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_cipher_fi	1.000m	49.563us	280	350	80.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	49.563us	280	350	80.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.883m	2.303ms	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_ctr_fi	1.000m	94.415us	44	50	88.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_cipher_fi	1.000m	49.563us	280	350	80.00
		aes_ctr_fi	1.000m	94.415us	44	50	88.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.667m	298.276us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_cipher_fi	1.000m	49.563us	280	350	80.00
		aes_ctr_fi	1.000m	94.415us	44	50	88.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_cipher_fi	1.000m	49.563us	280	350	80.00
		aes_ctr_fi	1.000m	94.415us	44	50	88.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_ctr_fi	1.000m	94.415us	44	50	88.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.883m	2.303ms	50	50	100.00
		aes_control_fi	1.000m	51.902us	242	300	80.67
		aes_cipher_fi	1.000m	49.563us	280	350	80.00
V2S		TOTAL			848	985	86.09
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	42.000s	725.368us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1454	1602	90.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.35	98.55	96.32	99.42	95.82	97.72	97.78	99.11	96.41

Failure Buckets

Job timed out after * minutes has 128 failures:
- Test aes_control_fi has 55 failures.
  - 13.aes_control_fi.106618128025048445746980477714505636263545332201022394725461435290622747990087
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 18.aes_control_fi.16659476712782710510877806838900949358839190895362108297367871694435096342638
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 53 more failures.
- Test aes_cipher_fi has 67 failures.
  - 13.aes_cipher_fi.50808150469362295841177013682412301606957239016074214185609280921579591517786
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_cipher_fi.74138687251275904261836817940844064432807567846630312540061438927616279390916
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 65 more failures.
- Test aes_ctr_fi has 6 failures.
  - 13.aes_ctr_fi.40036643315144608332516951341839873038923048038079562814784260321579829447250
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/13.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_ctr_fi.99587449306810985840931848362827832610479663466796044391947874411581470707413
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/14.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.27018499887617105874042389752224429618465846557910147603039833132572755335172
Line 725, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 725367821 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 725367821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.27786119582259860578809446857935068849384873162031589377774444971174039398006
Line 263, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 186704574 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 186704574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 10.aes_cipher_fi.60045759930422888997833779764969853484423022972433187089092620264880790014594
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007446853 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007446853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 72.aes_cipher_fi.73591024376935517229893843504666293295810191598820664405880511474909524058848
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10027499548 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027499548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 18.aes_core_fi.65009209765533810651309359301477806452803423592316819298609681369892985825123
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011207660 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011207660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.aes_core_fi.1264453594615320547866432860428260907330562420240587514506489922649364108793
    Line 143, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022059545 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022059545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 89.aes_control_fi.45455656814500410764101827684766531754622071450380462602036497418418994955690
    Line 123, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/89.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008605176 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008605176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 164.aes_control_fi.75219912088193102355035076354466205579033523118641850076160999809623071340692
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/164.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014564417 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014564417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:868) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 8.aes_stress_all_with_rand_reset.21835741074656481832825679063167277681389038245121082117039177994673378976057
    Line 155, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 126332323 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 126332323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.95923195127575901713049811541110150183999341973801285525725973028430601451331
    Line 144, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 226923867 ps: (cip_base_vseq.sv:868) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 226923867 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.55780260900525549324986356396561391148404984638501366037111759508138860581853
    Line 144, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  90275457 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  90275457 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.38542152061236847989064980673880716853653919788168357937658509226395677698379
    Line 1012, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 932574162 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 932574162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_scoreboard.sv:714) scoreboard [scoreboard] has 1 failures:
- Test aes_clear has 1 failures.
  - 17.aes_clear.17782808651609557315371968219433042587297781949563359804849565933230552468269
    Line 13005, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_masked-sim-xcelium/17.aes_clear/latest/run.log
```
  UVM_FATAL @ 196025812 ps: (aes_scoreboard.sv:714) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
       ----| SAW TOO MANY MESSAGES AND NONE WAS SPLIT
       ----| Expected:           2
       ----| Seen:               3
       ----| Expected corrupted: 0
```