83db9403d
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | wake_up | aes_wake_up | 3.000s | 54.376us | 1 | 1 | 100.00 |
V1 | smoke | aes_smoke | 5.000s | 116.586us | 50 | 50 | 100.00 |
V1 | csr_hw_reset | aes_csr_hw_reset | 4.000s | 64.558us | 5 | 5 | 100.00 |
V1 | csr_rw | aes_csr_rw | 4.000s | 102.738us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | aes_csr_bit_bash | 14.000s | 7.242ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | aes_csr_aliasing | 5.000s | 332.856us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 4.000s | 118.939us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 4.000s | 102.738us | 20 | 20 | 100.00 |
aes_csr_aliasing | 5.000s | 332.856us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 106 | 106 | 100.00 | |||
V2 | algorithm | aes_smoke | 5.000s | 116.586us | 50 | 50 | 100.00 |
aes_config_error | 5.000s | 67.993us | 50 | 50 | 100.00 | ||
aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 | ||
V2 | key_length | aes_smoke | 5.000s | 116.586us | 50 | 50 | 100.00 |
aes_config_error | 5.000s | 67.993us | 50 | 50 | 100.00 | ||
aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 | ||
V2 | back2back | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
aes_b2b | 12.000s | 134.978us | 50 | 50 | 100.00 | ||
V2 | backpressure | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
V2 | multi_message | aes_smoke | 5.000s | 116.586us | 50 | 50 | 100.00 |
aes_config_error | 5.000s | 67.993us | 50 | 50 | 100.00 | ||
aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 | ||
aes_alert_reset | 6.000s | 298.281us | 49 | 50 | 98.00 | ||
V2 | failure_test | aes_config_error | 5.000s | 67.993us | 50 | 50 | 100.00 |
aes_alert_reset | 6.000s | 298.281us | 49 | 50 | 98.00 | ||
aes_man_cfg_err | 5.000s | 57.390us | 50 | 50 | 100.00 | ||
V2 | trigger_clear_test | aes_clear | 7.000s | 167.609us | 50 | 50 | 100.00 |
V2 | nist_test_vectors | aes_nist_vectors | 7.000s | 306.771us | 1 | 1 | 100.00 |
V2 | reset_recovery | aes_alert_reset | 6.000s | 298.281us | 49 | 50 | 98.00 |
V2 | stress | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
V2 | sideload | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
aes_sideload | 7.000s | 188.892us | 50 | 50 | 100.00 | ||
V2 | deinitialization | aes_deinit | 7.000s | 281.119us | 50 | 50 | 100.00 |
V2 | alert_test | aes_alert_test | 5.000s | 68.577us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | aes_tl_errors | 6.000s | 408.206us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | aes_tl_errors | 6.000s | 408.206us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | aes_csr_hw_reset | 4.000s | 64.558us | 5 | 5 | 100.00 |
aes_csr_rw | 4.000s | 102.738us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 5.000s | 332.856us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 4.000s | 309.047us | 20 | 20 | 100.00 | ||
V2 | tl_d_partial_access | aes_csr_hw_reset | 4.000s | 64.558us | 5 | 5 | 100.00 |
aes_csr_rw | 4.000s | 102.738us | 20 | 20 | 100.00 | ||
aes_csr_aliasing | 5.000s | 332.856us | 5 | 5 | 100.00 | ||
aes_same_csr_outstanding | 4.000s | 309.047us | 20 | 20 | 100.00 | ||
V2 | TOTAL | 490 | 491 | 99.80 | |||
V2S | reseeding | aes_reseed | 42.000s | 2.049ms | 49 | 50 | 98.00 |
V2S | fault_inject | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 | ||
V2S | shadow_reg_update_error | aes_shadow_reg_errors | 4.000s | 76.742us | 20 | 20 | 100.00 |
V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 4.000s | 76.742us | 20 | 20 | 100.00 |
V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 4.000s | 76.742us | 20 | 20 | 100.00 |
V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 4.000s | 76.742us | 20 | 20 | 100.00 |
V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 5.000s | 213.964us | 20 | 20 | 100.00 |
V2S | tl_intg_err | aes_sec_cm | 9.000s | 1.299ms | 5 | 5 | 100.00 |
aes_tl_intg_err | 6.000s | 531.219us | 20 | 20 | 100.00 | ||
V2S | sec_cm_bus_integrity | aes_tl_intg_err | 6.000s | 531.219us | 20 | 20 | 100.00 |
V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 6.000s | 298.281us | 49 | 50 | 98.00 |
V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 4.000s | 76.742us | 20 | 20 | 100.00 |
V2S | sec_cm_main_config_sparse | aes_smoke | 5.000s | 116.586us | 50 | 50 | 100.00 |
aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 | ||
aes_alert_reset | 6.000s | 298.281us | 49 | 50 | 98.00 | ||
aes_core_fi | 5.850m | 10.011ms | 69 | 70 | 98.57 | ||
V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 4.000s | 76.742us | 20 | 20 | 100.00 |
V2S | sec_cm_aux_config_regwen | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
aes_readability | 4.000s | 126.087us | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sideload | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
aes_sideload | 7.000s | 188.892us | 50 | 50 | 100.00 | ||
V2S | sec_cm_key_sw_unreadable | aes_readability | 4.000s | 126.087us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 4.000s | 126.087us | 50 | 50 | 100.00 |
V2S | sec_cm_key_sec_wipe | aes_readability | 4.000s | 126.087us | 50 | 50 | 100.00 |
V2S | sec_cm_iv_config_sec_wipe | aes_readability | 4.000s | 126.087us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_sec_wipe | aes_readability | 4.000s | 126.087us | 50 | 50 | 100.00 |
V2S | sec_cm_data_reg_key_sca | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
V2S | sec_cm_key_masking | aes_stress | 36.000s | 929.205us | 50 | 50 | 100.00 |
V2S | sec_cm_main_fsm_sparse | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
V2S | sec_cm_main_fsm_redun | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 | ||
aes_ctr_fi | 5.000s | 73.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_cipher_fsm_sparse | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
V2S | sec_cm_cipher_fsm_redun | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 | ||
V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 |
V2S | sec_cm_ctr_fsm_sparse | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
V2S | sec_cm_ctr_fsm_redun | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_ctr_fi | 5.000s | 73.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_ctrl_sparse | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 | ||
aes_ctr_fi | 5.000s | 73.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 6.000s | 298.281us | 49 | 50 | 98.00 |
V2S | sec_cm_main_fsm_local_esc | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 | ||
aes_ctr_fi | 5.000s | 73.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 | ||
aes_ctr_fi | 5.000s | 73.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_ctr_fi | 5.000s | 73.664us | 49 | 50 | 98.00 | ||
V2S | sec_cm_data_reg_local_esc | aes_fi | 7.000s | 327.994us | 49 | 50 | 98.00 |
aes_control_fi | 48.000s | 16.270ms | 275 | 300 | 91.67 | ||
aes_cipher_fi | 46.000s | 10.004ms | 321 | 350 | 91.71 | ||
V2S | TOTAL | 927 | 985 | 94.11 | |||
V3 | TOTAL | 0 | 0 | -- | |||
TOTAL | 1523 | 1582 | 96.27 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 12 | 12 | 11 | 91.67 |
V2S | 11 | 11 | 5 | 45.45 |
Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
---|---|---|---|---|---|---|---|---|
97.14 | 97.58 | 94.52 | 98.83 | 93.60 | 97.72 | 91.11 | 98.26 | 92.09 |
Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out
has 31 failures:
0.aes_control_fi.1480976593
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
Job ID: smart:5e7f98c7-9582-4f24-9e26-c6652bc9c8fe
6.aes_control_fi.1826115050
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
Job ID: smart:9e272470-21f1-4b08-afe7-f54858e6dac5
... and 14 more failures.
1.aes_cipher_fi.4196250693
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
Job ID: smart:c9e92936-60ea-4074-a24c-cc33262535ba
8.aes_cipher_fi.2156936123
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
Job ID: smart:2e3d9623-0e24-4591-83a4-bb7f3cdf5db8
... and 12 more failures.
37.aes_ctr_fi.2189895302
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_ctr_fi/latest/run.log
Job ID: smart:ab89ddb1-3daa-41f2-aaa4-8da456f053f7
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!
has 15 failures:
10.aes_cipher_fi.1243922158
Line 274, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10007344679 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10007344679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
53.aes_cipher_fi.1857572787
Line 279, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_cipher_fi/latest/run.log
UVM_FATAL @ 10005184649 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
UVM_INFO @ 10005184649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!
has 9 failures:
140.aes_control_fi.2984444594
Line 277, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/140.aes_control_fi/latest/run.log
UVM_FATAL @ 10014625725 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10014625725 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
184.aes_control_fi.3315190663
Line 282, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/184.aes_control_fi/latest/run.log
UVM_FATAL @ 10011875788 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
UVM_INFO @ 10011875788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 7 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,978): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS)
has 1 failures:
9.aes_alert_reset.2803099003
Line 1741, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_alert_reset/latest/run.log
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,978): (time 40326152 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 40259485 PS)
($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
|
xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,984): (time 40326152 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 40259485 PS)
UVM_ERROR @ 40326152 ps: (aes_core.sv:978) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset
has 1 failures:
19.aes_fi.1242831418
Line 3843, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_fi/latest/run.log
UVM_FATAL @ 15076362 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
UVM_INFO @ 15076362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:621) scoreboard [scoreboard] # *
has 1 failures:
30.aes_reseed.1585378609
Line 1199, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_reseed/latest/run.log
UVM_FATAL @ 8111333 ps: (aes_scoreboard.sv:621) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] # 0
TEST FAILED MESSAGES DID NOT MATCH
0 b5 74 fa 0
1 00 f2 c1 0
UVM_FATAL (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == *
has 1 failures:
53.aes_core_fi.2831122349
Line 272, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
UVM_FATAL @ 10010734394 ps: (csr_utils_pkg.sv:567) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x912e584) == 0x0
UVM_INFO @ 10010734394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---