AES/UNMASKED Simulation Results

Thursday March 28 2024 19:02:20 UTC

GitHub Revision: `4ee21f808f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29834210046083588839632889378999422318513504283488100050460647435812066910143

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	77.426us	1	1	100.00
V1	smoke	aes_smoke	8.000s	71.881us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	170.510us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	130.751us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	804.983us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	123.345us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	61.491us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	130.751us	20	20	100.00
		aes_csr_aliasing	6.000s	123.345us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	71.881us	50	50	100.00
		aes_config_error	8.000s	250.455us	50	50	100.00
		aes_stress	9.000s	58.863us	50	50	100.00
V2	key_length	aes_smoke	8.000s	71.881us	50	50	100.00
		aes_config_error	8.000s	250.455us	50	50	100.00
		aes_stress	9.000s	58.863us	50	50	100.00
V2	back2back	aes_stress	9.000s	58.863us	50	50	100.00
		aes_b2b	12.000s	209.349us	50	50	100.00
V2	backpressure	aes_stress	9.000s	58.863us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	71.881us	50	50	100.00
		aes_config_error	8.000s	250.455us	50	50	100.00
		aes_stress	9.000s	58.863us	50	50	100.00
		aes_alert_reset	13.000s	154.933us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	142.243us	50	50	100.00
		aes_config_error	8.000s	250.455us	50	50	100.00
		aes_alert_reset	13.000s	154.933us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	592.429us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	388.638us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	154.933us	50	50	100.00
V2	stress	aes_stress	9.000s	58.863us	50	50	100.00
V2	sideload	aes_stress	9.000s	58.863us	50	50	100.00
		aes_sideload	5.000s	102.954us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	139.056us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	837.299us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	56.219us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	265.395us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	265.395us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	170.510us	5	5	100.00
		aes_csr_rw	7.000s	130.751us	20	20	100.00
		aes_csr_aliasing	6.000s	123.345us	5	5	100.00
		aes_same_csr_outstanding	4.000s	78.241us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	170.510us	5	5	100.00
		aes_csr_rw	7.000s	130.751us	20	20	100.00
		aes_csr_aliasing	6.000s	123.345us	5	5	100.00
		aes_same_csr_outstanding	4.000s	78.241us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	66.836us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_cipher_fi	49.000s	31.533ms	321	350	91.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	84.489us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	84.489us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	84.489us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	84.489us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	385.028us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.207ms	5	5	100.00
		aes_tl_intg_err	5.000s	171.538us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	171.538us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	154.933us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	84.489us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	71.881us	50	50	100.00
		aes_stress	9.000s	58.863us	50	50	100.00
		aes_alert_reset	13.000s	154.933us	50	50	100.00
		aes_core_fi	25.000s	10.023ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	84.489us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	54.445us	50	50	100.00
		aes_stress	9.000s	58.863us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	58.863us	50	50	100.00
		aes_sideload	5.000s	102.954us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	54.445us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	54.445us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	54.445us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	54.445us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	54.445us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	58.863us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	58.863us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	64.094us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_cipher_fi	49.000s	31.533ms	321	350	91.71
		aes_ctr_fi	9.000s	54.788us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	64.094us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_cipher_fi	49.000s	31.533ms	321	350	91.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	31.533ms	321	350	91.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	64.094us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_ctr_fi	9.000s	54.788us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_cipher_fi	49.000s	31.533ms	321	350	91.71
		aes_ctr_fi	9.000s	54.788us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	154.933us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_cipher_fi	49.000s	31.533ms	321	350	91.71
		aes_ctr_fi	9.000s	54.788us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_cipher_fi	49.000s	31.533ms	321	350	91.71
		aes_ctr_fi	9.000s	54.788us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_ctr_fi	9.000s	54.788us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	64.094us	49	50	98.00
		aes_control_fi	47.000s	65.650ms	272	300	90.67
		aes_cipher_fi	49.000s	31.533ms	321	350	91.71
V2S		TOTAL			925	985	93.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.883m	9.256ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1532	1602	95.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.40	94.13	98.83	93.59	97.64	91.85	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_cipher_fi has 12 failures.
  - 16.aes_cipher_fi.105364529455008888645281441560816121904990079679252875297209203058831816627668
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  Job ID: smart:7d330a02-4db3-4086-b493-1ff8f7e86f1b
```
  - 135.aes_cipher_fi.38543196301254047504818562450310831875896240343494035688015280107814046391664
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/135.aes_cipher_fi/latest/run.log
```
  Job ID: smart:80e3682b-e82d-4462-b7e7-d92bcc2f6a18
```
  - ... and 10 more failures.
- Test aes_control_fi has 17 failures.
  - 30.aes_control_fi.46213661208127969397995352489243083723595569803092107392661306932061783740345
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  Job ID: smart:2809184a-a070-4c85-bada-2b5705629fdb
```
  - 51.aes_control_fi.39041009539220666730331183672001030248254297460445077483030616469984334075804
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:f6a8ef8e-e565-47ba-8c4a-3b59614f8d97
```
  - ... and 15 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 17 failures:
- Test aes_cipher_fi has 17 failures.
  - 78.aes_cipher_fi.89913098668407206299164114342513062416954986537536492844321245138064034614695
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010572347 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010572347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 93.aes_cipher_fi.81421539105671181534606489828960914449217057662704114108662854844006728601522
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/93.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006949810 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006949810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 44.aes_control_fi.22328626375747049355827137015701184356048980198591762166887879027040631069171
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004286371 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004286371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_control_fi.83377166653120117058221249654379467673515508576064128140796879025290112665807
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10027485067 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027485067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.108836197391033881849049910126032671173336686622168613889457963706564836385699
Line 968, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4403435370 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4403435370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.94837757490144264135577897719365598881373752493560368005249398681118610043313
Line 572, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9256191008 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9256191008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 7.aes_core_fi.40495658779324235752775648156182424333302976390205727277088532221296585389390
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10045006188 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10045006188 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 38.aes_core_fi.95672742977496775263660929211527290565363453117698066111436826853038717941295
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022624967 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022624967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 30.aes_fi.13985616494626026628866357705028350249626642715747658593133433159897790725240
    Line 1558, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 7137114 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 7127013 PS)
  UVM_ERROR @   7137114 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   7137114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```