AES/UNMASKED Simulation Results

Sunday March 31 2024 19:03:23 UTC

GitHub Revision: `919341eb22`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 80856351313811177568455658403012118288310064949310327557570531903004064389549

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	64.140us	1	1	100.00
V1	smoke	aes_smoke	9.000s	74.869us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	59.783us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	127.095us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	1.097ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	460.021us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	82.544us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	127.095us	20	20	100.00
		aes_csr_aliasing	4.000s	460.021us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	74.869us	50	50	100.00
		aes_config_error	13.000s	114.183us	50	50	100.00
		aes_stress	9.000s	101.194us	50	50	100.00
V2	key_length	aes_smoke	9.000s	74.869us	50	50	100.00
		aes_config_error	13.000s	114.183us	50	50	100.00
		aes_stress	9.000s	101.194us	50	50	100.00
V2	back2back	aes_stress	9.000s	101.194us	50	50	100.00
		aes_b2b	12.000s	256.698us	50	50	100.00
V2	backpressure	aes_stress	9.000s	101.194us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	74.869us	50	50	100.00
		aes_config_error	13.000s	114.183us	50	50	100.00
		aes_stress	9.000s	101.194us	50	50	100.00
		aes_alert_reset	9.000s	76.902us	50	50	100.00
V2	failure_test	aes_man_cfg_err	9.000s	75.689us	50	50	100.00
		aes_config_error	13.000s	114.183us	50	50	100.00
		aes_alert_reset	9.000s	76.902us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	63.849us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	308.824us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	76.902us	50	50	100.00
V2	stress	aes_stress	9.000s	101.194us	50	50	100.00
V2	sideload	aes_stress	9.000s	101.194us	50	50	100.00
		aes_sideload	9.000s	67.571us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	62.424us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	1.134ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	67.764us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	205.375us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	205.375us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	59.783us	5	5	100.00
		aes_csr_rw	4.000s	127.095us	20	20	100.00
		aes_csr_aliasing	4.000s	460.021us	5	5	100.00
		aes_same_csr_outstanding	4.000s	308.334us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	59.783us	5	5	100.00
		aes_csr_rw	4.000s	127.095us	20	20	100.00
		aes_csr_aliasing	4.000s	460.021us	5	5	100.00
		aes_same_csr_outstanding	4.000s	308.334us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	9.000s	73.535us	49	50	98.00
V2S	fault_inject	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_cipher_fi	45.000s	32.170ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	69.451us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	69.451us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	69.451us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	69.451us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	256.703us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	903.207us	5	5	100.00
		aes_tl_intg_err	5.000s	254.519us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	254.519us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	76.902us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	69.451us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	74.869us	50	50	100.00
		aes_stress	9.000s	101.194us	50	50	100.00
		aes_alert_reset	9.000s	76.902us	50	50	100.00
		aes_core_fi	1.783m	10.037ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	69.451us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	125.673us	50	50	100.00
		aes_stress	9.000s	101.194us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	101.194us	50	50	100.00
		aes_sideload	9.000s	67.571us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	125.673us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	125.673us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	125.673us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	125.673us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	125.673us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	101.194us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	101.194us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	107.931us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_cipher_fi	45.000s	32.170ms	329	350	94.00
		aes_ctr_fi	8.000s	92.514us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	107.931us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_cipher_fi	45.000s	32.170ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	32.170ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	107.931us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_ctr_fi	8.000s	92.514us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_cipher_fi	45.000s	32.170ms	329	350	94.00
		aes_ctr_fi	8.000s	92.514us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	76.902us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_cipher_fi	45.000s	32.170ms	329	350	94.00
		aes_ctr_fi	8.000s	92.514us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_cipher_fi	45.000s	32.170ms	329	350	94.00
		aes_ctr_fi	8.000s	92.514us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_ctr_fi	8.000s	92.514us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	107.931us	50	50	100.00
		aes_control_fi	53.000s	27.184ms	273	300	91.00
		aes_cipher_fi	45.000s	32.170ms	329	350	94.00
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	2.886ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.22	97.46	94.25	98.87	93.71	97.72	93.33	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 16 failures.
  - 9.aes_control_fi.82681715806662311454691796506569329648917819389927883672317457810657338207387
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:9e5a002d-b1d0-45f5-ba92-906238da8371
```
  - 17.aes_control_fi.51259734302000768814272800886486832496010097128404415306190781026004615154902
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:97640c06-686a-41f1-9f0c-358a9a2e7072
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 14 failures.
  - 18.aes_cipher_fi.86649653556949256011181032566730755001641176320750431135490712226482320720371
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2243d797-0d21-43f0-884f-755446874d32
```
  - 41.aes_cipher_fi.45627538429419798790981381936943621983862406403404129258027818793679848829529
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9d7524d7-63ee-41bd-b6d5-8034f3c1984c
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 11.aes_control_fi.38655313856212002841053428096472565321571869996625717500978781030609972441124
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10014911281 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014911281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 69.aes_control_fi.16636208639579547191970629009037168312331081922945490384541638243066173787057
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/69.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020304719 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020304719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 5.aes_cipher_fi.24711097978144185476918858697706685539000663701882881832256867855158929870312
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007072977 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007072977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_cipher_fi.73542699251418843453816539950405304690591977738286423061582202816199031405803
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011623922 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011623922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

3.aes_stress_all_with_rand_reset.100226636152827025061396397467415958726421204962216354086432842303391831286921
Line 825, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 497760144 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 497760144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.62714146447635293587389353791931624027680665543721315928858437206770863874885
Line 968, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 274454068 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 274454068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.78172678530851978619008606025102244951531148202959095788903078610524752387138
Line 1660, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1713534604 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1713534604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.75159096301884635413799169854745225707516389190797007874722358603864443492216
Line 401, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2886055160 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2886055160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 2.aes_core_fi.48389648621835095914635772323490541447108851894066634264182307912976668764865
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002794163 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002794163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.109530584259047099381278706218725161141518665698518408219928191074383489017131
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004955734 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004955734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 3 failures:
- Test aes_core_fi has 3 failures.
  - 10.aes_core_fi.11010116914898121404688139536360427499361862716759969235888463249224241662506
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10036978264 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x63b41984) == 0x0
  UVM_INFO @ 10036978264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.49270443846041909871648401189010030736259826281635180593528709566415533046895
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10089770031 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x22a81584) == 0x0
  UVM_INFO @ 10089770031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.11304004436899336791734586581947125754308538911262970859381813172872083056243
    Line 476, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 118315044 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 118295044 PS)
  UVM_ERROR @ 118315044 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 118315044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 13.aes_reseed.51773978248395806060486521331665333173674528422639686528412740372261265313235
    Line 391, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_reseed/latest/run.log
```
  UVM_FATAL @  21844420 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  21844420 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 195.aes_cipher_fi.36820082509803147268951748883293882300565253642776029673318468525713931884322
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/195.aes_cipher_fi/latest/run.log
```
  UVM_ERROR @   7900153 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @   7900153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```