AES/UNMASKED Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: `41bc3e0c7f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	80.750us	1	1	100.00
V1	smoke	aes_smoke	11.000s	117.400us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	156.376us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	72.724us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	6.000s	322.095us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	428.286us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	77.950us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	72.724us	20	20	100.00
		aes_csr_aliasing	5.000s	428.286us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	11.000s	117.400us	50	50	100.00
		aes_config_error	10.000s	98.810us	50	50	100.00
		aes_stress	9.000s	233.958us	50	50	100.00
V2	key_length	aes_smoke	11.000s	117.400us	50	50	100.00
		aes_config_error	10.000s	98.810us	50	50	100.00
		aes_stress	9.000s	233.958us	50	50	100.00
V2	back2back	aes_stress	9.000s	233.958us	50	50	100.00
		aes_b2b	10.000s	121.106us	50	50	100.00
V2	backpressure	aes_stress	9.000s	233.958us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	117.400us	50	50	100.00
		aes_config_error	10.000s	98.810us	50	50	100.00
		aes_stress	9.000s	233.958us	50	50	100.00
		aes_alert_reset	8.000s	167.208us	49	50	98.00
V2	failure_test	aes_man_cfg_err	4.000s	59.018us	50	50	100.00
		aes_config_error	10.000s	98.810us	50	50	100.00
		aes_alert_reset	8.000s	167.208us	49	50	98.00
V2	trigger_clear_test	aes_clear	10.000s	179.989us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	170.907us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	167.208us	49	50	98.00
V2	stress	aes_stress	9.000s	233.958us	50	50	100.00
V2	sideload	aes_stress	9.000s	233.958us	50	50	100.00
		aes_sideload	9.000s	76.962us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	96.106us	50	50	100.00
V2	stress_all	aes_stress_all	32.000s	910.824us	10	10	100.00
V2	alert_test	aes_alert_test	17.000s	64.700us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	214.040us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	214.040us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	156.376us	5	5	100.00
		aes_csr_rw	4.000s	72.724us	20	20	100.00
		aes_csr_aliasing	5.000s	428.286us	5	5	100.00
		aes_same_csr_outstanding	3.333m	10.015ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	156.376us	5	5	100.00
		aes_csr_rw	4.000s	72.724us	20	20	100.00
		aes_csr_aliasing	5.000s	428.286us	5	5	100.00
		aes_same_csr_outstanding	3.333m	10.015ms	19	20	95.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	11.000s	222.571us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_cipher_fi	48.000s	31.529ms	331	350	94.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	61.112us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	61.112us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	61.112us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	61.112us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	91.132us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.441ms	5	5	100.00
		aes_tl_intg_err	5.000s	157.120us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	157.120us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	167.208us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	61.112us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	117.400us	50	50	100.00
		aes_stress	9.000s	233.958us	50	50	100.00
		aes_alert_reset	8.000s	167.208us	49	50	98.00
		aes_core_fi	37.000s	10.008ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	61.112us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	238.527us	50	50	100.00
		aes_stress	9.000s	233.958us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	233.958us	50	50	100.00
		aes_sideload	9.000s	76.962us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	238.527us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	238.527us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	238.527us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	238.527us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	238.527us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	233.958us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	233.958us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	485.313us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_cipher_fi	48.000s	31.529ms	331	350	94.57
		aes_ctr_fi	10.000s	130.642us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	485.313us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_cipher_fi	48.000s	31.529ms	331	350	94.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	31.529ms	331	350	94.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	485.313us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_ctr_fi	10.000s	130.642us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_cipher_fi	48.000s	31.529ms	331	350	94.57
		aes_ctr_fi	10.000s	130.642us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	167.208us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_cipher_fi	48.000s	31.529ms	331	350	94.57
		aes_ctr_fi	10.000s	130.642us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_cipher_fi	48.000s	31.529ms	331	350	94.57
		aes_ctr_fi	10.000s	130.642us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_ctr_fi	10.000s	130.642us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	485.313us	50	50	100.00
		aes_control_fi	48.000s	16.274ms	272	300	90.67
		aes_cipher_fi	48.000s	31.529ms	331	350	94.57
V2S		TOTAL			937	985	95.13
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.550m	36.321ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1541	1602	96.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	11	84.62
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.39	94.17	98.73	93.77	97.64	91.11	98.85	96.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 25 failures:
- Test aes_control_fi has 15 failures.
  - 17.aes_control_fi.15500988579871557501823417011781565191295500934901171373707215484966681081964
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:9afee4ca-09cc-4a48-ae6d-732ba108c1e2
```
  - 19.aes_control_fi.113343304316150279351008882598771491578349432704468041779105040798157341964492
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:e7c7181e-409e-435a-916e-6f306ee181c7
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 10 failures.
  - 60.aes_cipher_fi.112563591738293920367692657555006201357659683273151827207694298143381187236217
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  Job ID: smart:57870300-bfd7-45c0-821d-7ad1357c1656
```
  - 98.aes_cipher_fi.53488910175198936153893150114137050955603904173484500789263701162268719527063
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/98.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9259edff-627f-4e97-9bb1-1e20e123cfa7
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 2.aes_control_fi.14310017803649790952179158015350052325821038820000637701020553208269212668135
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012792080 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012792080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.aes_control_fi.62872382431187681137579492625145627803904613638464232186205612863601180374971
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020660508 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020660508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 24.aes_cipher_fi.62920129786498796195309366487278702802662297918745292096142961538851295582756
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004334359 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004334359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 90.aes_cipher_fi.70177768341666713207110417112153530544490142498167925440086539800178597239585
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/90.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025289920 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025289920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.85249195285895293837863949311167778243814470161778177909288368827852323026647
Line 1218, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5494042306 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5494042306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.74729478367127747624173744628215618962393520739898272946918702618302796815775
Line 715, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1090808943 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1090808943 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.40720096924157579138683578395454149301550265460371946341006979953520348919298
Line 1940, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3242220108 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3242220108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.88741429180190120343622325709070465332865748837828912838572789103868375321093
Line 1268, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2188362572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2188362572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

9.aes_alert_reset.7654243233542151857786652418759106835077888163054279982359324717230328921963
Line 1469, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 18232864 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 18192864 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 18232864 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 18192864 PS)
  UVM_ERROR @  18232864 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 13.aes_same_csr_outstanding.83686483083112599361359372689514851992305841629382136463954100699147927816667
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10015399108 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xfbfaa784) == 0x0
  UVM_INFO @ 10015399108 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 14.aes_csr_mem_rw_with_rand_reset.20599899015727394856611378887402945149142482343985765548453547457029500654530
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 443713889 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 443713889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 17.aes_core_fi.93502896303407623034465560617838901246664850195733924192749578155120432521387
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007836733 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007836733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```