AES/UNMASKED Simulation Results

Thursday April 11 2024 19:07:25 UTC

GitHub Revision: `1f410ef5dc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 77676901304510083363507443373754332549719316834151559528665885252978172929472

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	82.697us	1	1	100.00
V1	smoke	aes_smoke	10.000s	131.070us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	85.982us	5	5	100.00
V1	csr_rw	aes_csr_rw	5.000s	55.572us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	1.112ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	1.106ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	1.667ms	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	5.000s	55.572us	20	20	100.00
		aes_csr_aliasing	5.000s	1.106ms	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	10.000s	131.070us	50	50	100.00
		aes_config_error	20.000s	440.282us	50	50	100.00
		aes_stress	6.000s	105.565us	50	50	100.00
V2	key_length	aes_smoke	10.000s	131.070us	50	50	100.00
		aes_config_error	20.000s	440.282us	50	50	100.00
		aes_stress	6.000s	105.565us	50	50	100.00
V2	back2back	aes_stress	6.000s	105.565us	50	50	100.00
		aes_b2b	15.000s	116.399us	50	50	100.00
V2	backpressure	aes_stress	6.000s	105.565us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	131.070us	50	50	100.00
		aes_config_error	20.000s	440.282us	50	50	100.00
		aes_stress	6.000s	105.565us	50	50	100.00
		aes_alert_reset	10.000s	125.606us	50	50	100.00
V2	failure_test	aes_man_cfg_err	7.000s	117.326us	50	50	100.00
		aes_config_error	20.000s	440.282us	50	50	100.00
		aes_alert_reset	10.000s	125.606us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	108.572us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	174.357us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	125.606us	50	50	100.00
V2	stress	aes_stress	6.000s	105.565us	50	50	100.00
V2	sideload	aes_stress	6.000s	105.565us	50	50	100.00
		aes_sideload	9.000s	114.640us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	1.193ms	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	1.906ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	149.843us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	208.089us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	208.089us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	85.982us	5	5	100.00
		aes_csr_rw	5.000s	55.572us	20	20	100.00
		aes_csr_aliasing	5.000s	1.106ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	706.905us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	85.982us	5	5	100.00
		aes_csr_rw	5.000s	55.572us	20	20	100.00
		aes_csr_aliasing	5.000s	1.106ms	5	5	100.00
		aes_same_csr_outstanding	4.000s	706.905us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	13.000s	109.274us	50	50	100.00
V2S	fault_inject	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_cipher_fi	51.000s	43.774ms	314	350	89.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	219.759us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	219.759us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	219.759us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	219.759us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	139.297us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.736ms	5	5	100.00
		aes_tl_intg_err	6.000s	767.130us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	767.130us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	125.606us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	219.759us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	131.070us	50	50	100.00
		aes_stress	6.000s	105.565us	50	50	100.00
		aes_alert_reset	10.000s	125.606us	50	50	100.00
		aes_core_fi	48.000s	10.014ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	219.759us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	10.000s	61.896us	50	50	100.00
		aes_stress	6.000s	105.565us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	105.565us	50	50	100.00
		aes_sideload	9.000s	114.640us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	10.000s	61.896us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	10.000s	61.896us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	10.000s	61.896us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	10.000s	61.896us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	10.000s	61.896us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	105.565us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	105.565us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	18.000s	67.626us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_cipher_fi	51.000s	43.774ms	314	350	89.71
		aes_ctr_fi	8.000s	148.717us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	18.000s	67.626us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_cipher_fi	51.000s	43.774ms	314	350	89.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	43.774ms	314	350	89.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	18.000s	67.626us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_ctr_fi	8.000s	148.717us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_cipher_fi	51.000s	43.774ms	314	350	89.71
		aes_ctr_fi	8.000s	148.717us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	125.606us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_cipher_fi	51.000s	43.774ms	314	350	89.71
		aes_ctr_fi	8.000s	148.717us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_cipher_fi	51.000s	43.774ms	314	350	89.71
		aes_ctr_fi	8.000s	148.717us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_ctr_fi	8.000s	148.717us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	18.000s	67.626us	49	50	98.00
		aes_control_fi	43.000s	10.005ms	279	300	93.00
		aes_cipher_fi	51.000s	43.774ms	314	350	89.71
V2S		TOTAL			923	985	93.71
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.017m	5.675ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1528	1602	95.38

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.39	94.09	98.83	93.65	97.72	91.11	98.85	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 35 failures:
- Test aes_cipher_fi has 23 failures.
  - 14.aes_cipher_fi.26538585988248961192549214104906468484678624813516358914895100434769994060159
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:43963edb-cc5a-407d-8cbb-c9978c807183
```
  - 15.aes_cipher_fi.54161361774838576669110307315510641016481709066415854821865833365802481576683
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5e1a7a42-9b25-4ebd-b37d-4dfe0ff00b59
```
  - ... and 21 more failures.
- Test aes_control_fi has 12 failures.
  - 37.aes_control_fi.87693380082885669666512246982471371285667092166398763754311782396819689669974
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_control_fi/latest/run.log
```
  Job ID: smart:ec8b47b8-2a85-4e2d-96a9-1b3a483197ef
```
  - 88.aes_control_fi.105236045086810906471566555584211974506652432839564535369918364945493496141935
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/88.aes_control_fi/latest/run.log
```
  Job ID: smart:c7822e5a-a7dc-41bb-ad63-201874648a8d
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 40.aes_cipher_fi.72081241827337745500471633781904559485701619774694742471713263804654538561276
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007831921 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007831921 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_cipher_fi.55727824645307526563241350892829825433931401360194688077559127723038114317342
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003089277 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003089277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 18.aes_control_fi.65400429460798736449227801775472601888863050795791368074308925976596240923644
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007434056 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007434056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 26.aes_control_fi.72139216930567244053209269144574293641904839923172165085089616103318060221766
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10025546492 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025546492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.9698265286853647635984505543840867708367147228796954764416894233880058954702
Line 1132, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 901939162 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 901939162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.81266644961774215810705927567258687762885892705884497817104772522648238088385
Line 1231, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3885156809 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3885156809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

5.aes_stress_all_with_rand_reset.21621961600638069835692806812120398801780510792240338369547073385739173882509
Line 694, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 536201722 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 536201722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.107019200758425659229512361114384038985487665928582554816106564984783715023809
Line 1667, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3477944352 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3477944352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 1.aes_core_fi.19717363041665735750712144428221092313601523736404885342869813899200884947742
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009206182 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009206182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_core_fi.35371922347001634467132261393123538325957879607705212710420159077246587208103
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009133842 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009133842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 12.aes_core_fi.51508110653710473172697390719677771478483354836738294160053815955311523777082
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10038784746 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10038784746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 51.aes_core_fi.43431927463994807684605532096559811430265061226971050419454096347943997723215
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014388032 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014388032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 4.aes_fi.45850027282034286153313605780211238050402942649544350745090784530805699889329
    Line 6425, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_fi/latest/run.log
```
  UVM_FATAL @ 405859125 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 405859125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 7.aes_csr_mem_rw_with_rand_reset.31467933977228746692965831661782639585848573214980949862194762753606400256245
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1666875206 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1666875206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

8.aes_stress_all.92942192201818234303264659103272118441384511720784896997947556398765203592980
Line 7299, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 43635418 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 43625418 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 43635418 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 43625418 PS)
  UVM_ERROR @  43635418 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut