9f4903e77a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | wake_up | aes_wake_up | 0 | 1 | 0.00 | ||
| V1 | smoke | aes_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | aes_csr_hw_reset | 7.000s | 61.300us | 5 | 5 | 100.00 |
| V1 | csr_rw | aes_csr_rw | 1.483m | 10.016ms | 19 | 20 | 95.00 |
| V1 | csr_bit_bash | aes_csr_bit_bash | 11.000s | 3.058ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aes_csr_aliasing | 9.000s | 115.419us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aes_csr_mem_rw_with_rand_reset | 9.000s | 69.459us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aes_csr_rw | 1.483m | 10.016ms | 19 | 20 | 95.00 |
| aes_csr_aliasing | 9.000s | 115.419us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 54 | 106 | 50.94 | |||
| V2 | algorithm | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | key_length | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2 | back2back | aes_stress | 0 | 50 | 0.00 | ||
| aes_b2b | 0 | 50 | 0.00 | ||||
| V2 | backpressure | aes_stress | 0 | 50 | 0.00 | ||
| V2 | multi_message | aes_smoke | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | failure_test | aes_man_cfg_err | 0 | 50 | 0.00 | ||
| aes_config_error | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| V2 | trigger_clear_test | aes_clear | 0 | 50 | 0.00 | ||
| V2 | nist_test_vectors | aes_nist_vectors | 0 | 1 | 0.00 | ||
| V2 | reset_recovery | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2 | stress | aes_stress | 0 | 50 | 0.00 | ||
| V2 | sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2 | deinitialization | aes_deinit | 0 | 50 | 0.00 | ||
| V2 | stress_all | aes_stress_all | 0 | 10 | 0.00 | ||
| V2 | alert_test | aes_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | aes_tl_errors | 9.000s | 334.577us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aes_tl_errors | 9.000s | 334.577us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aes_csr_hw_reset | 7.000s | 61.300us | 5 | 5 | 100.00 |
| aes_csr_rw | 1.483m | 10.016ms | 19 | 20 | 95.00 | ||
| aes_csr_aliasing | 9.000s | 115.419us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 9.000s | 223.789us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aes_csr_hw_reset | 7.000s | 61.300us | 5 | 5 | 100.00 |
| aes_csr_rw | 1.483m | 10.016ms | 19 | 20 | 95.00 | ||
| aes_csr_aliasing | 9.000s | 115.419us | 5 | 5 | 100.00 | ||
| aes_same_csr_outstanding | 9.000s | 223.789us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 40 | 501 | 7.98 | |||
| V2S | reseeding | aes_reseed | 0 | 50 | 0.00 | ||
| V2S | fault_inject | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | shadow_reg_update_error | aes_shadow_reg_errors | 13.000s | 65.650us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | aes_shadow_reg_errors | 13.000s | 65.650us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | aes_shadow_reg_errors | 13.000s | 65.650us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | aes_shadow_reg_errors | 13.000s | 65.650us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | aes_shadow_reg_errors_with_csr_rw | 14.000s | 123.935us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | aes_sec_cm | 0 | 5 | 0.00 | ||
| aes_tl_intg_err | 13.000s | 149.532us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aes_tl_intg_err | 13.000s | 149.532us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_config_shadow | aes_shadow_reg_errors | 13.000s | 65.650us | 20 | 20 | 100.00 |
| V2S | sec_cm_main_config_sparse | aes_smoke | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| aes_alert_reset | 0 | 50 | 0.00 | ||||
| aes_core_fi | 0 | 70 | 0.00 | ||||
| V2S | sec_cm_aux_config_shadow | aes_shadow_reg_errors | 13.000s | 65.650us | 20 | 20 | 100.00 |
| V2S | sec_cm_aux_config_regwen | aes_readability | 0 | 50 | 0.00 | ||
| aes_stress | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sideload | aes_stress | 0 | 50 | 0.00 | ||
| aes_sideload | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_key_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sw_unreadable | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_iv_config_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_sec_wipe | aes_readability | 0 | 50 | 0.00 | ||
| V2S | sec_cm_data_reg_key_sca | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_key_masking | aes_stress | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_cipher_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | sec_cm_cipher_ctr_redun | aes_cipher_fi | 0 | 350 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_sparse | aes_fi | 0 | 50 | 0.00 | ||
| V2S | sec_cm_ctr_fsm_redun | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctrl_sparse | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_main_fsm_global_esc | aes_alert_reset | 0 | 50 | 0.00 | ||
| V2S | sec_cm_main_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_cipher_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_ctr_fsm_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_ctr_fi | 0 | 50 | 0.00 | ||||
| V2S | sec_cm_data_reg_local_esc | aes_fi | 0 | 50 | 0.00 | ||
| aes_control_fi | 0 | 300 | 0.00 | ||||
| aes_cipher_fi | 0 | 350 | 0.00 | ||||
| V2S | TOTAL | 60 | 985 | 6.09 | |||
| V3 | stress_all_with_rand_reset | aes_stress_all_with_rand_reset | 0 | 10 | 0.00 | ||
| V3 | TOTAL | 0 | 10 | 0.00 | |||
| TOTAL | 154 | 1602 | 9.61 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 7 | 7 | 4 | 57.14 |
| V2 | 13 | 13 | 2 | 15.38 |
| V2S | 11 | 11 | 3 | 27.27 |
| V3 | 1 | 1 | 0 | 0.00 |
| Score | Block | Branch | Statement | Expression | Toggle | Fsm | Assertion | CoverGroup |
|---|---|---|---|---|---|---|---|---|
| 84.10 | 99.63 | 98.89 | 100.00 | 99.74 | 44.47 | -- | 98.03 | 43.64 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 724 failures:
Test aes_wake_up has 1 failures.
Test aes_deinit has 28 failures.
0.aes_deinit.111910503288794483192379173974275815189620965934690096703039049895321318518659
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_deinit/latest/run.log
1.aes_deinit.83058100665960145848544121435508874958527539481294201150907365235177441290612
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_deinit/latest/run.log
... and 26 more failures.
Test aes_readability has 28 failures.
0.aes_readability.8581210962428314096789068190400963966062761328478126496976601626895540982301
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_readability/latest/run.log
1.aes_readability.29730667393992744186013090925244324000450205027792155785041681116267703627893
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_readability/latest/run.log
... and 26 more failures.
Test aes_config_error has 28 failures.
0.aes_config_error.96899173806564427993179883751906590252480449700637150635829440882042115612545
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_config_error/latest/run.log
1.aes_config_error.101746903452683349574449524424778207191076304604803011118381642068312468947605
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_config_error/latest/run.log
... and 26 more failures.
Test aes_b2b has 28 failures.
0.aes_b2b.59270502982070356955692044314455515678938895875961086365819515510900233409019
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_b2b/latest/run.log
1.aes_b2b.88843143946791082494660399822590393637501717155791912861509129624552816470490
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_b2b/latest/run.log
... and 26 more failures.
... and 16 more tests.
Job killed most likely because its dependent job failed. has 723 failures:
Test aes_nist_vectors has 1 failures.
Test aes_man_cfg_err has 28 failures.
0.aes_man_cfg_err.47051585177003599335829460200606417937447494383629929709467875492518047435907
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_man_cfg_err/latest/run.log
1.aes_man_cfg_err.23965593553806530810605215199943860628678732078687520699297990068472736689050
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_man_cfg_err/latest/run.log
... and 26 more failures.
Test aes_smoke has 28 failures.
0.aes_smoke.40333530780143650587678478974326744324026096797187495839720470459037860465857
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_smoke/latest/run.log
1.aes_smoke.46283158811114512850715813281369555206288758922171441601780280263966562192535
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_smoke/latest/run.log
... and 26 more failures.
Test aes_stress has 28 failures.
0.aes_stress.76432192111335447249876956533871113739362815456708328626198582502092764282850
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress/latest/run.log
1.aes_stress.49082875037337287811503876153926402450840285045449759043328832691264418354553
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress/latest/run.log
... and 26 more failures.
Test aes_clear has 28 failures.
0.aes_clear.89317920067961786672284886917718150968677691972541388691973184136409385083672
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_clear/latest/run.log
1.aes_clear.17958257559544535616632081480337926812197074230346558347833333650672716181345
Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_clear/latest/run.log
... and 26 more failures.
... and 15 more tests.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
16.aes_csr_rw.18456405233723074497054692197494536015325011128774804834065648751910337634011
Line 286, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_csr_rw/latest/run.log
UVM_FATAL @ 10016087186 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xd5e1ab84) == 0x0
UVM_INFO @ 10016087186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---