AES/UNMASKED Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: `7773b039d0`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	248.471us	1	1	100.00
V1	smoke	aes_smoke	14.000s	76.657us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	98.477us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	61.271us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	703.442us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	68.532us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	81.524us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	61.271us	20	20	100.00
		aes_csr_aliasing	9.000s	68.532us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	76.657us	50	50	100.00
		aes_config_error	13.000s	83.282us	50	50	100.00
		aes_stress	15.000s	321.904us	50	50	100.00
V2	key_length	aes_smoke	14.000s	76.657us	50	50	100.00
		aes_config_error	13.000s	83.282us	50	50	100.00
		aes_stress	15.000s	321.904us	50	50	100.00
V2	back2back	aes_stress	15.000s	321.904us	50	50	100.00
		aes_b2b	25.000s	209.292us	50	50	100.00
V2	backpressure	aes_stress	15.000s	321.904us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	76.657us	50	50	100.00
		aes_config_error	13.000s	83.282us	50	50	100.00
		aes_stress	15.000s	321.904us	50	50	100.00
		aes_alert_reset	13.000s	65.966us	50	50	100.00
V2	failure_test	aes_man_cfg_err	12.000s	54.617us	50	50	100.00
		aes_config_error	13.000s	83.282us	50	50	100.00
		aes_alert_reset	13.000s	65.966us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	240.741us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	312.167us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	65.966us	50	50	100.00
V2	stress	aes_stress	15.000s	321.904us	50	50	100.00
V2	sideload	aes_stress	15.000s	321.904us	50	50	100.00
		aes_sideload	13.000s	58.058us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	138.367us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	10.470ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	109.832us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	81.141us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	81.141us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	98.477us	5	5	100.00
		aes_csr_rw	8.000s	61.271us	20	20	100.00
		aes_csr_aliasing	9.000s	68.532us	5	5	100.00
		aes_same_csr_outstanding	1.433m	10.039ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	98.477us	5	5	100.00
		aes_csr_rw	8.000s	61.271us	20	20	100.00
		aes_csr_aliasing	9.000s	68.532us	5	5	100.00
		aes_same_csr_outstanding	1.433m	10.039ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	19.000s	163.477us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_cipher_fi	43.000s	10.013ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	67.819us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	67.819us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	67.819us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	67.819us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	196.504us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.840ms	5	5	100.00
		aes_tl_intg_err	14.000s	596.765us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	596.765us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	65.966us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	67.819us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	76.657us	50	50	100.00
		aes_stress	15.000s	321.904us	50	50	100.00
		aes_alert_reset	13.000s	65.966us	50	50	100.00
		aes_core_fi	45.000s	10.002ms	62	70	88.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	67.819us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	14.000s	121.862us	50	50	100.00
		aes_stress	15.000s	321.904us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	321.904us	50	50	100.00
		aes_sideload	13.000s	58.058us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	14.000s	121.862us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	14.000s	121.862us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	14.000s	121.862us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	14.000s	121.862us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	14.000s	121.862us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	321.904us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	321.904us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	102.796us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_cipher_fi	43.000s	10.013ms	325	350	92.86
		aes_ctr_fi	13.000s	78.780us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	102.796us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_cipher_fi	43.000s	10.013ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	43.000s	10.013ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	102.796us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_ctr_fi	13.000s	78.780us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_cipher_fi	43.000s	10.013ms	325	350	92.86
		aes_ctr_fi	13.000s	78.780us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	65.966us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_cipher_fi	43.000s	10.013ms	325	350	92.86
		aes_ctr_fi	13.000s	78.780us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_cipher_fi	43.000s	10.013ms	325	350	92.86
		aes_ctr_fi	13.000s	78.780us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_ctr_fi	13.000s	78.780us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	102.796us	50	50	100.00
		aes_control_fi	51.000s	10.004ms	279	300	93.00
		aes_cipher_fi	43.000s	10.013ms	325	350	92.86
V2S		TOTAL			931	985	94.52
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.833m	9.351ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.44	94.21	98.85	93.88	97.72	91.11	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 12 failures.
  - 9.aes_control_fi.55266789847764472829070554136173746939120494006664199287208659856763901098978
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  Job ID: smart:a7e5b623-6a0c-445c-b95d-9f44108f5781
```
  - 45.aes_control_fi.86619138245302077181592874639689122632724349797461933531029500177149059050228
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_control_fi/latest/run.log
```
  Job ID: smart:4c729b9a-e311-4727-ba58-77355a721ab4
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 18 failures.
  - 20.aes_cipher_fi.39792144872293202373155541556402205506907146626118989360265091429434973442397
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9b48665b-665e-4feb-a5ff-cbe1eb3d7ce1
```
  - 22.aes_cipher_fi.26424614766422636951882582201349711462638011864357045638899414162476614807350
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9fdc344c-633f-4d91-93a2-9cba48ad2222
```
  - ... and 16 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 43.aes_control_fi.106371006909842631876069163860169773406518968670451108737554095225435020287238
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10032659477 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10032659477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 90.aes_control_fi.55826452856889610747182898017195364405618853772177143886158431606572291550466
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/90.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008288587 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008288587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_core_fi has 7 failures.
  - 8.aes_core_fi.89659991550495146829346232621675136829520623599783684668200180342516043643457
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007699240 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007699240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_core_fi.32239220508331703239866641042111315020544275967543758487745446337423987285347
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002139505 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002139505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 43.aes_cipher_fi.111160470834320897276401844850657568398094853963285540412917902946246447268357
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10022761230 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022761230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_cipher_fi.99942160281201645032821160682784149103265778740077421404308986804668784726119
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013382609 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013382609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.57366425695792124792812123898848799124206500032892207040410179600074195277512
Line 796, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 17389547390 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 17389547390 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.113445272042770066868924084676681454172069665628483661416649894656700078266432
Line 1182, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 788472629 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 788472629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.43206980648034921970795472171839059930527361328687435489491457157102066514289
Line 1180, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 566879344 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 566879344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aes_stress_all_with_rand_reset.2361096414104807855356118935184128997802494038171249461888461082260535695174
Line 1448, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 767858967 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 767858967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 5.aes_stress_all_with_rand_reset.39244919179682629998928682871967071333002740882190847033975092456208060482252
    Line 1138, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 17819455955 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 17819455955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.9202297613128298011675911387439991933339436631086594961857527372785342904591
    Line 386, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 561961517 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 561961517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 4.aes_same_csr_outstanding.77386698050859799338013096448488946658850921254992815585708178267782409437685
    Line 288, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10038918651 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x5198e984) == 0x0
  UVM_INFO @ 10038918651 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 30.aes_core_fi.88597323241490924199373100374857069317648581546910069174623684675022045831882
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10042907774 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10042907774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```