AES/UNMASKED Simulation Results

Sunday April 07 2024 19:02:41 UTC

GitHub Revision: 7773b039d0

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 110372901762865644007400082009110088154180821215015477169464044145224727696933

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 4.000s 248.471us 1 1 100.00
V1 smoke aes_smoke 14.000s 76.657us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 3.000s 98.477us 5 5 100.00
V1 csr_rw aes_csr_rw 8.000s 61.271us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 9.000s 703.442us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 9.000s 68.532us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 13.000s 81.524us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 8.000s 61.271us 20 20 100.00
aes_csr_aliasing 9.000s 68.532us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 14.000s 76.657us 50 50 100.00
aes_config_error 13.000s 83.282us 50 50 100.00
aes_stress 15.000s 321.904us 50 50 100.00
V2 key_length aes_smoke 14.000s 76.657us 50 50 100.00
aes_config_error 13.000s 83.282us 50 50 100.00
aes_stress 15.000s 321.904us 50 50 100.00
V2 back2back aes_stress 15.000s 321.904us 50 50 100.00
aes_b2b 25.000s 209.292us 50 50 100.00
V2 backpressure aes_stress 15.000s 321.904us 50 50 100.00
V2 multi_message aes_smoke 14.000s 76.657us 50 50 100.00
aes_config_error 13.000s 83.282us 50 50 100.00
aes_stress 15.000s 321.904us 50 50 100.00
aes_alert_reset 13.000s 65.966us 50 50 100.00
V2 failure_test aes_man_cfg_err 12.000s 54.617us 50 50 100.00
aes_config_error 13.000s 83.282us 50 50 100.00
aes_alert_reset 13.000s 65.966us 50 50 100.00
V2 trigger_clear_test aes_clear 14.000s 240.741us 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 6.000s 312.167us 1 1 100.00
V2 reset_recovery aes_alert_reset 13.000s 65.966us 50 50 100.00
V2 stress aes_stress 15.000s 321.904us 50 50 100.00
V2 sideload aes_stress 15.000s 321.904us 50 50 100.00
aes_sideload 13.000s 58.058us 50 50 100.00
V2 deinitialization aes_deinit 15.000s 138.367us 50 50 100.00
V2 stress_all aes_stress_all 34.000s 10.470ms 10 10 100.00
V2 alert_test aes_alert_test 13.000s 109.832us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 15.000s 81.141us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 15.000s 81.141us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 3.000s 98.477us 5 5 100.00
aes_csr_rw 8.000s 61.271us 20 20 100.00
aes_csr_aliasing 9.000s 68.532us 5 5 100.00
aes_same_csr_outstanding 1.433m 10.039ms 19 20 95.00
V2 tl_d_partial_access aes_csr_hw_reset 3.000s 98.477us 5 5 100.00
aes_csr_rw 8.000s 61.271us 20 20 100.00
aes_csr_aliasing 9.000s 68.532us 5 5 100.00
aes_same_csr_outstanding 1.433m 10.039ms 19 20 95.00
V2 TOTAL 500 501 99.80
V2S reseeding aes_reseed 19.000s 163.477us 50 50 100.00
V2S fault_inject aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_cipher_fi 43.000s 10.013ms 325 350 92.86
V2S shadow_reg_update_error aes_shadow_reg_errors 13.000s 67.819us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 13.000s 67.819us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 13.000s 67.819us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 13.000s 67.819us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 9.000s 196.504us 20 20 100.00
V2S tl_intg_err aes_sec_cm 10.000s 1.840ms 5 5 100.00
aes_tl_intg_err 14.000s 596.765us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 14.000s 596.765us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 13.000s 65.966us 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 13.000s 67.819us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 14.000s 76.657us 50 50 100.00
aes_stress 15.000s 321.904us 50 50 100.00
aes_alert_reset 13.000s 65.966us 50 50 100.00
aes_core_fi 45.000s 10.002ms 62 70 88.57
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 13.000s 67.819us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 14.000s 121.862us 50 50 100.00
aes_stress 15.000s 321.904us 50 50 100.00
V2S sec_cm_key_sideload aes_stress 15.000s 321.904us 50 50 100.00
aes_sideload 13.000s 58.058us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 14.000s 121.862us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 14.000s 121.862us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 14.000s 121.862us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 14.000s 121.862us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 14.000s 121.862us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 15.000s 321.904us 50 50 100.00
V2S sec_cm_key_masking aes_stress 15.000s 321.904us 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 14.000s 102.796us 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_cipher_fi 43.000s 10.013ms 325 350 92.86
aes_ctr_fi 13.000s 78.780us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 14.000s 102.796us 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_cipher_fi 43.000s 10.013ms 325 350 92.86
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 43.000s 10.013ms 325 350 92.86
V2S sec_cm_ctr_fsm_sparse aes_fi 14.000s 102.796us 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_ctr_fi 13.000s 78.780us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_cipher_fi 43.000s 10.013ms 325 350 92.86
aes_ctr_fi 13.000s 78.780us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 13.000s 65.966us 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_cipher_fi 43.000s 10.013ms 325 350 92.86
aes_ctr_fi 13.000s 78.780us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_cipher_fi 43.000s 10.013ms 325 350 92.86
aes_ctr_fi 13.000s 78.780us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_ctr_fi 13.000s 78.780us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 14.000s 102.796us 50 50 100.00
aes_control_fi 51.000s 10.004ms 279 300 93.00
aes_cipher_fi 43.000s 10.013ms 325 350 92.86
V2S TOTAL 931 985 94.52
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 3.833m 9.351ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1537 1602 95.94

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 12 92.31
V2S 11 11 8 72.73
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.20 97.44 94.21 98.85 93.88 97.72 91.11 98.66 96.01

Failure Buckets

Past Results