AES/UNMASKED Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	136.510us	1	1	100.00
V1	smoke	aes_smoke	14.000s	98.004us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	89.333us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	60.576us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	2.411ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	9.000s	165.046us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	95.938us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	60.576us	20	20	100.00
		aes_csr_aliasing	9.000s	165.046us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	98.004us	50	50	100.00
		aes_config_error	16.000s	59.919us	50	50	100.00
		aes_stress	18.000s	159.643us	50	50	100.00
V2	key_length	aes_smoke	14.000s	98.004us	50	50	100.00
		aes_config_error	16.000s	59.919us	50	50	100.00
		aes_stress	18.000s	159.643us	50	50	100.00
V2	back2back	aes_stress	18.000s	159.643us	50	50	100.00
		aes_b2b	18.000s	76.436us	50	50	100.00
V2	backpressure	aes_stress	18.000s	159.643us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	98.004us	50	50	100.00
		aes_config_error	16.000s	59.919us	50	50	100.00
		aes_stress	18.000s	159.643us	50	50	100.00
		aes_alert_reset	16.000s	73.856us	50	50	100.00
V2	failure_test	aes_man_cfg_err	15.000s	94.631us	50	50	100.00
		aes_config_error	16.000s	59.919us	50	50	100.00
		aes_alert_reset	16.000s	73.856us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	291.316us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	136.731us	1	1	100.00
V2	reset_recovery	aes_alert_reset	16.000s	73.856us	50	50	100.00
V2	stress	aes_stress	18.000s	159.643us	50	50	100.00
V2	sideload	aes_stress	18.000s	159.643us	50	50	100.00
		aes_sideload	14.000s	61.720us	50	50	100.00
V2	deinitialization	aes_deinit	17.000s	65.641us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	9.792ms	9	10	90.00
V2	alert_test	aes_alert_test	13.000s	59.019us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	461.409us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	461.409us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	89.333us	5	5	100.00
		aes_csr_rw	7.000s	60.576us	20	20	100.00
		aes_csr_aliasing	9.000s	165.046us	5	5	100.00
		aes_same_csr_outstanding	8.000s	59.796us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	89.333us	5	5	100.00
		aes_csr_rw	7.000s	60.576us	20	20	100.00
		aes_csr_aliasing	9.000s	165.046us	5	5	100.00
		aes_same_csr_outstanding	8.000s	59.796us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	12.000s	104.267us	50	50	100.00
V2S	fault_inject	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_cipher_fi	49.000s	16.114ms	333	350	95.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	63.221us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	63.221us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	63.221us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	63.221us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	3.350m	10.045ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	10.000s	3.440ms	5	5	100.00
		aes_tl_intg_err	5.000s	225.617us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	225.617us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	16.000s	73.856us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	63.221us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	98.004us	50	50	100.00
		aes_stress	18.000s	159.643us	50	50	100.00
		aes_alert_reset	16.000s	73.856us	50	50	100.00
		aes_core_fi	2.200m	10.032ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	63.221us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	15.000s	50.945us	50	50	100.00
		aes_stress	18.000s	159.643us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	159.643us	50	50	100.00
		aes_sideload	14.000s	61.720us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	15.000s	50.945us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	15.000s	50.945us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	15.000s	50.945us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	15.000s	50.945us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	15.000s	50.945us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	159.643us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	159.643us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	11.000s	73.389us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_cipher_fi	49.000s	16.114ms	333	350	95.14
		aes_ctr_fi	11.000s	166.580us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	11.000s	73.389us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_cipher_fi	49.000s	16.114ms	333	350	95.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	16.114ms	333	350	95.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	11.000s	73.389us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_ctr_fi	11.000s	166.580us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_cipher_fi	49.000s	16.114ms	333	350	95.14
		aes_ctr_fi	11.000s	166.580us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	16.000s	73.856us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_cipher_fi	49.000s	16.114ms	333	350	95.14
		aes_ctr_fi	11.000s	166.580us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_cipher_fi	49.000s	16.114ms	333	350	95.14
		aes_ctr_fi	11.000s	166.580us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_ctr_fi	11.000s	166.580us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	11.000s	73.389us	50	50	100.00
		aes_control_fi	47.000s	16.444ms	269	300	89.67
		aes_cipher_fi	49.000s	16.114ms	333	350	95.14
V2S		TOTAL			931	985	94.52
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	5.117m	20.635ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	97.39	94.09	98.77	93.88	97.72	91.11	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_cipher_fi has 10 failures.
  - 2.aes_cipher_fi.57441343915350558542621593386664935510674132656633026080274100055973708486864
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:11f127fb-6283-4935-8ea5-f4686fdc4535
```
  - 78.aes_cipher_fi.50893758765021871029796345503355915218833564366885778784976632235750986009117
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/78.aes_cipher_fi/latest/run.log
```
  Job ID: smart:43500bd1-21c7-4ca0-b528-11331db6cdc0
```
  - ... and 8 more failures.
- Test aes_control_fi has 18 failures.
  - 13.aes_control_fi.5229542722596821471704487273998754413862234610644067424450866253351286264588
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:8e3dcc2f-9c46-4578-93e5-13c667216100
```
  - 34.aes_control_fi.110385890810225552070068102148059206026039594729551813868627502245910230220199
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  Job ID: smart:43ef479a-cbd3-48b9-b70f-f4af0f51631f
```
  - ... and 16 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_control_fi has 13 failures.
  - 19.aes_control_fi.24013350982879906400355518233214217860481793143821292203087745918060602204707
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10010975922 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010975922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_control_fi.23051177466125629846482246328274617183261197635450823196033844051743501198468
    Line 328, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10041360523 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10041360523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 5.aes_cipher_fi.31278005348100792405859224147889439602516054789758824122230301076976945822836
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011770752 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011770752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_cipher_fi.37297891895083593843399490713843542213630732040801632747517182714947960005521
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005048102 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005048102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.105275917862671072995733427946467519530795125765462628244942213820948548117398
Line 443, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1219390675 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1219390675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.86982688519014285463900773719020292376156838503991556517475644347630997315231
Line 922, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 676084853 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 676084853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

3.aes_stress_all_with_rand_reset.23348237702828062415637848970569829500132575307109542750692979665390171108641
Line 724, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 724191477 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 724191477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.84741937601116548779390813631693798400285396707548528070510459551635590450795
Line 559, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 112058345 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 112058345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 0.aes_core_fi.72984260946391512140741938166408924516586288648514690976810845492682236964334
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010795835 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010795835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.aes_core_fi.59478578518689073761976665024144753907390935606976319000018986864550443536380
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10020495113 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020495113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_stress_all_with_rand_reset has 1 failures.

2.aes_stress_all_with_rand_reset.47149590563627992887947459326861826778842596156336201428768668738814526324442
Line 1639, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 1753067117 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 1753027117 PS)
  UVM_ERROR @ 1753067117 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 1753067117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aes_stress_all has 1 failures.

9.aes_stress_all.1687126844484953194822987809577465436135875206047499403288762074536574802004
Line 49462, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 3090360249 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 3090320249 PS)
  UVM_ERROR @ 3090360249 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 3090360249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 2 failures:
- Test aes_core_fi has 2 failures.
  - 7.aes_core_fi.11370604682616666176423257596111940075654849088499735502491919114515016222118
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10038788379 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x88ceb584) == 0x0
  UVM_INFO @ 10038788379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_core_fi.44999116132511013143910626105855463661857524424005130055006761851171982996754
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10032472913 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1a81684) == 0x0
  UVM_INFO @ 10032472913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.88240291862833385517601396255021635218193032029485959490139470403255192049741
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 169121321 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 169121321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 14.aes_shadow_reg_errors_with_csr_rw.93098568668476782907086978221199519101663163962593136655106965983267174721758
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10045414866 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xd6b4a084) == 0x0
  UVM_INFO @ 10045414866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 36.aes_core_fi.77560693945608102236730818732134967555442709591587313912299844992354736490920
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015571125 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015571125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```