AES/UNMASKED Simulation Results

Thursday April 04 2024 19:02:33 UTC

GitHub Revision: `2723ca659d`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9870132716819564205271541124341458297216848204999383102382742091236484427981

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	60.760us	1	1	100.00
V1	smoke	aes_smoke	4.000s	57.534us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	55.376us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	78.795us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	4.940ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	160.161us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	271.454us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	78.795us	20	20	100.00
		aes_csr_aliasing	6.000s	160.161us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	57.534us	50	50	100.00
		aes_config_error	9.000s	81.168us	50	50	100.00
		aes_stress	7.000s	239.915us	50	50	100.00
V2	key_length	aes_smoke	4.000s	57.534us	50	50	100.00
		aes_config_error	9.000s	81.168us	50	50	100.00
		aes_stress	7.000s	239.915us	50	50	100.00
V2	back2back	aes_stress	7.000s	239.915us	50	50	100.00
		aes_b2b	10.000s	297.565us	50	50	100.00
V2	backpressure	aes_stress	7.000s	239.915us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	57.534us	50	50	100.00
		aes_config_error	9.000s	81.168us	50	50	100.00
		aes_stress	7.000s	239.915us	50	50	100.00
		aes_alert_reset	5.000s	668.476us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	55.114us	50	50	100.00
		aes_config_error	9.000s	81.168us	50	50	100.00
		aes_alert_reset	5.000s	668.476us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	423.405us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	181.353us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	668.476us	50	50	100.00
V2	stress	aes_stress	7.000s	239.915us	50	50	100.00
V2	sideload	aes_stress	7.000s	239.915us	50	50	100.00
		aes_sideload	5.000s	220.588us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	151.122us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	8.782ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	57.998us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	825.168us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	825.168us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	55.376us	5	5	100.00
		aes_csr_rw	4.000s	78.795us	20	20	100.00
		aes_csr_aliasing	6.000s	160.161us	5	5	100.00
		aes_same_csr_outstanding	34.000s	10.181ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	55.376us	5	5	100.00
		aes_csr_rw	4.000s	78.795us	20	20	100.00
		aes_csr_aliasing	6.000s	160.161us	5	5	100.00
		aes_same_csr_outstanding	34.000s	10.181ms	19	20	95.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	6.000s	961.295us	50	50	100.00
V2S	fault_inject	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_cipher_fi	50.000s	92.667ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	63.226us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	63.226us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	63.226us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	63.226us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	91.631us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.036ms	5	5	100.00
		aes_tl_intg_err	7.000s	133.065us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	133.065us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	668.476us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	63.226us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	57.534us	50	50	100.00
		aes_stress	7.000s	239.915us	50	50	100.00
		aes_alert_reset	5.000s	668.476us	50	50	100.00
		aes_core_fi	3.483m	10.019ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	63.226us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	208.351us	50	50	100.00
		aes_stress	7.000s	239.915us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	239.915us	50	50	100.00
		aes_sideload	5.000s	220.588us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	208.351us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	208.351us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	208.351us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	208.351us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	208.351us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	239.915us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	239.915us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	6.000s	261.082us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_cipher_fi	50.000s	92.667ms	320	350	91.43
		aes_ctr_fi	4.000s	177.601us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	6.000s	261.082us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_cipher_fi	50.000s	92.667ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	92.667ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	6.000s	261.082us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_ctr_fi	4.000s	177.601us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_cipher_fi	50.000s	92.667ms	320	350	91.43
		aes_ctr_fi	4.000s	177.601us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	668.476us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_cipher_fi	50.000s	92.667ms	320	350	91.43
		aes_ctr_fi	4.000s	177.601us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_cipher_fi	50.000s	92.667ms	320	350	91.43
		aes_ctr_fi	4.000s	177.601us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_ctr_fi	4.000s	177.601us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	6.000s	261.082us	49	50	98.00
		aes_control_fi	44.000s	10.003ms	282	300	94.00
		aes_cipher_fi	50.000s	92.667ms	320	350	91.43
V2S		TOTAL			932	985	94.62
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.750m	9.141ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1538	1602	96.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.37	94.04	98.83	93.57	97.64	91.85	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 9 failures.
  - 0.aes_control_fi.102963536713012073567330803320988635730833124771312079254726836774104390041822
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:f7bee5ba-ebda-46df-bd17-958c4658eba2
```
  - 21.aes_control_fi.79877040109890382537746395251003182030266551399087998684098600171126764208559
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  Job ID: smart:bc88164e-694b-425a-968f-2f7509e23383
```
  - ... and 7 more failures.
- Test aes_cipher_fi has 19 failures.
  - 10.aes_cipher_fi.65979829450422021542415433055487844055428890376412910000247289957203952741448
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job ID: smart:758229aa-5071-4f86-a29a-84af1d461ced
```
  - 19.aes_cipher_fi.16651878787073125636410364962032473701948932951638453641676794219987961508705
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:4ee0ef8c-6692-4b9e-8ca4-b8d580f79649
```
  - ... and 17 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 4.aes_cipher_fi.5991117739612881012249896122402641845897771187006976228817669291201792913102
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009329987 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009329987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_cipher_fi.63223347649132187044764041881654742869366756282030195686364568024529798854737
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006058292 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006058292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 55.aes_control_fi.6773078165562598487009958832989099546795863428317599750195703613586598931308
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/55.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011300693 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011300693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 140.aes_control_fi.10957587204740727870130208697673372209220866083186263733114665531529445780239
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/140.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011389480 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011389480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.90395627388284479708067426601211763636574488105573609124171946227755226531915
Line 1025, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1431716669 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1431716669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.68864226520535337044804530740276742074008013612374480339281121825665189497473
Line 880, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2186695788 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2186695788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 3 failures:
- Test aes_core_fi has 3 failures.
  - 22.aes_core_fi.102266405321756597373140475759550618425288873562621849667179053673897321965681
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019260183 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xaa51a884) == 0x0
  UVM_INFO @ 10019260183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_core_fi.42980402828363131734657976081224266410608281787912212333186150414741903939460
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10031096901 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x1c9a8c84) == 0x0
  UVM_INFO @ 10031096901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 0.aes_stress_all_with_rand_reset.110157638129115037674040780314698992002858621399673655597321175444877516868531
    Line 1471, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 743275161 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 743254753 PS)
  UVM_ERROR @ 743275161 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @ 743275161 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.81193901702684122233104362313328009915872212923615963168107633434481119420569
    Line 1542, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2131354054 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2131354054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 7.aes_core_fi.2715886250729347738433561811808812749021175009715424022864775661835252815340
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012997046 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012997046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 13.aes_same_csr_outstanding.11630018152379504920421137298318006177644779588787885334682365734162338871052
    Line 295, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10181169751 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x7f53c984) == 0x0
  UVM_INFO @ 10181169751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 39.aes_fi.79815581572581299457369445882901325870322577566975348791184534879439367789441
    Line 3990, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 12549758 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 12539758 PS)
  UVM_ERROR @  12549758 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  12549758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```