AES/UNMASKED Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: `d3942ca074`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	62.907us	1	1	100.00
V1	smoke	aes_smoke	9.000s	77.678us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	131.820us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	60.582us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	532.128us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	526.942us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	91.851us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	60.582us	20	20	100.00
		aes_csr_aliasing	6.000s	526.942us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	77.678us	50	50	100.00
		aes_config_error	13.000s	67.219us	50	50	100.00
		aes_stress	14.000s	195.181us	50	50	100.00
V2	key_length	aes_smoke	9.000s	77.678us	50	50	100.00
		aes_config_error	13.000s	67.219us	50	50	100.00
		aes_stress	14.000s	195.181us	50	50	100.00
V2	back2back	aes_stress	14.000s	195.181us	50	50	100.00
		aes_b2b	13.000s	1.350ms	50	50	100.00
V2	backpressure	aes_stress	14.000s	195.181us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	77.678us	50	50	100.00
		aes_config_error	13.000s	67.219us	50	50	100.00
		aes_stress	14.000s	195.181us	50	50	100.00
		aes_alert_reset	9.000s	70.983us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	68.562us	50	50	100.00
		aes_config_error	13.000s	67.219us	50	50	100.00
		aes_alert_reset	9.000s	70.983us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	97.678us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	289.137us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	70.983us	50	50	100.00
V2	stress	aes_stress	14.000s	195.181us	50	50	100.00
V2	sideload	aes_stress	14.000s	195.181us	50	50	100.00
		aes_sideload	9.000s	61.501us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	566.521us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	4.043ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	64.931us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	315.772us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	315.772us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	131.820us	5	5	100.00
		aes_csr_rw	3.000s	60.582us	20	20	100.00
		aes_csr_aliasing	6.000s	526.942us	5	5	100.00
		aes_same_csr_outstanding	5.000s	76.277us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	131.820us	5	5	100.00
		aes_csr_rw	3.000s	60.582us	20	20	100.00
		aes_csr_aliasing	6.000s	526.942us	5	5	100.00
		aes_same_csr_outstanding	5.000s	76.277us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	389.337us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_cipher_fi	48.000s	63.017ms	330	350	94.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	60.014us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	60.014us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	60.014us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	60.014us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	106.686us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	753.597us	5	5	100.00
		aes_tl_intg_err	6.000s	352.938us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	352.938us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	70.983us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	60.014us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	77.678us	50	50	100.00
		aes_stress	14.000s	195.181us	50	50	100.00
		aes_alert_reset	9.000s	70.983us	50	50	100.00
		aes_core_fi	6.283m	10.013ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	60.014us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	67.710us	50	50	100.00
		aes_stress	14.000s	195.181us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	195.181us	50	50	100.00
		aes_sideload	9.000s	61.501us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	67.710us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	67.710us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	67.710us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	67.710us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	67.710us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	195.181us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	195.181us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	147.774us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_cipher_fi	48.000s	63.017ms	330	350	94.29
		aes_ctr_fi	13.000s	106.961us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	147.774us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_cipher_fi	48.000s	63.017ms	330	350	94.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	63.017ms	330	350	94.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	147.774us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_ctr_fi	13.000s	106.961us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_cipher_fi	48.000s	63.017ms	330	350	94.29
		aes_ctr_fi	13.000s	106.961us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	70.983us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_cipher_fi	48.000s	63.017ms	330	350	94.29
		aes_ctr_fi	13.000s	106.961us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_cipher_fi	48.000s	63.017ms	330	350	94.29
		aes_ctr_fi	13.000s	106.961us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_ctr_fi	13.000s	106.961us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	147.774us	50	50	100.00
		aes_control_fi	50.000s	63.013ms	277	300	92.33
		aes_cipher_fi	48.000s	63.017ms	330	350	94.29
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	12.100m	113.173ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.42	94.17	98.83	93.74	97.72	91.11	98.66	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
- Test aes_control_fi has 16 failures.
  - 7.aes_control_fi.114864165695496786890228896157622829737895742820481849436226270751823839275926
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:26ffd5e3-aaa8-433c-a670-15fc762a9467
```
  - 20.aes_control_fi.96838999744378809311819066973634390898982433075432035325599874279894079662854
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:8748ee10-d40d-4c52-b1e2-6b4d2bc5692f
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 15 failures.
  - 18.aes_cipher_fi.88987143426950067670492231759264480294232282730169084572654229239760658516241
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  Job ID: smart:e215ca75-f601-4241-9eb1-b6b022845c91
```
  - 40.aes_cipher_fi.94808644996915994283202663116572515921171927171269246991661182086398990905403
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bfbb904a-97ee-4b70-9a11-7158708d4cb6
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 58.aes_control_fi.52679822498647077428390005680183449943826918363164805651086796426392989248965
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002317668 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002317668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 61.aes_control_fi.48033523474402808356586966276835784033373275407923101771782492615977354430457
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/61.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003094581 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003094581 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

1.aes_stress_all_with_rand_reset.20948697112523991181283995667280136400331617071041491597944039462165868980411
Line 792, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 113172660925 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 113172660925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.75337104939788266449714951615274914855790503085362051305422926312150691053376
Line 1248, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3453028159 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3453028159 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_cipher_fi has 5 failures.
  - 22.aes_cipher_fi.91233742983523895013056188933890281164167659662317081492699187693411471885620
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003341862 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003341862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_cipher_fi.5983991483251093359030168770657315298661283218294964386862321236812749689672
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006025409 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006025409 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 6.aes_core_fi.79158417519216031091030446030559163652807875323037964902225501213305667394979
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009307066 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009307066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.aes_core_fi.21713978023867394931807618548757178071227707734125039743204586760914385600201
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011517264 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011517264 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.89179487791686606240901444127237042501024297115394097992505068006009265348948
Line 1168, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 999556303 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 999556303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.56916179244692503228734623433811172107871944921752399311750335844032017468816
Line 964, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 245266585 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 245266585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.23544234228007394215613782068803876190657638598608957476124734303935800192389
    Line 410, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 162757532 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 162757532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 53.aes_core_fi.42128396203568125733898233320933044651356016932137820773574317280140559773960
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012590366 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd0e3d684) == 0x0
  UVM_INFO @ 10012590366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 57.aes_core_fi.56942500656865591620650298356548023149022581836035990470282753382335004631307
    Line 311, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10027689510 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10027689510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```