AES/UNMASKED Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	58.940us	1	1	100.00
V1	smoke	aes_smoke	25.000s	56.493us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	84.865us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	80.791us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	335.804us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.983m	10.059ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	114.621us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	80.791us	20	20	100.00
		aes_csr_aliasing	1.983m	10.059ms	4	5	80.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	25.000s	56.493us	50	50	100.00
		aes_config_error	15.000s	241.262us	50	50	100.00
		aes_stress	18.000s	55.950us	50	50	100.00
V2	key_length	aes_smoke	25.000s	56.493us	50	50	100.00
		aes_config_error	15.000s	241.262us	50	50	100.00
		aes_stress	18.000s	55.950us	50	50	100.00
V2	back2back	aes_stress	18.000s	55.950us	50	50	100.00
		aes_b2b	18.000s	127.107us	50	50	100.00
V2	backpressure	aes_stress	18.000s	55.950us	50	50	100.00
V2	multi_message	aes_smoke	25.000s	56.493us	50	50	100.00
		aes_config_error	15.000s	241.262us	50	50	100.00
		aes_stress	18.000s	55.950us	50	50	100.00
		aes_alert_reset	21.000s	141.624us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	70.552us	50	50	100.00
		aes_config_error	15.000s	241.262us	50	50	100.00
		aes_alert_reset	21.000s	141.624us	50	50	100.00
V2	trigger_clear_test	aes_clear	18.000s	653.125us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	169.202us	1	1	100.00
V2	reset_recovery	aes_alert_reset	21.000s	141.624us	50	50	100.00
V2	stress	aes_stress	18.000s	55.950us	50	50	100.00
V2	sideload	aes_stress	18.000s	55.950us	50	50	100.00
		aes_sideload	19.000s	78.777us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	95.738us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	1.027ms	10	10	100.00
V2	alert_test	aes_alert_test	19.000s	82.508us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	186.695us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	186.695us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	84.865us	5	5	100.00
		aes_csr_rw	8.000s	80.791us	20	20	100.00
		aes_csr_aliasing	1.983m	10.059ms	4	5	80.00
		aes_same_csr_outstanding	8.000s	61.974us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	84.865us	5	5	100.00
		aes_csr_rw	8.000s	80.791us	20	20	100.00
		aes_csr_aliasing	1.983m	10.059ms	4	5	80.00
		aes_same_csr_outstanding	8.000s	61.974us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	16.000s	267.914us	50	50	100.00
V2S	fault_inject	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_cipher_fi	45.000s	65.648ms	322	350	92.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	89.979us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	89.979us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	89.979us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	89.979us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	82.364us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	13.000s	473.652us	5	5	100.00
		aes_tl_intg_err	5.000s	520.748us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	520.748us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	21.000s	141.624us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	89.979us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	25.000s	56.493us	50	50	100.00
		aes_stress	18.000s	55.950us	50	50	100.00
		aes_alert_reset	21.000s	141.624us	50	50	100.00
		aes_core_fi	44.000s	10.003ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	89.979us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	19.000s	72.472us	50	50	100.00
		aes_stress	18.000s	55.950us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	18.000s	55.950us	50	50	100.00
		aes_sideload	19.000s	78.777us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	19.000s	72.472us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	19.000s	72.472us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	19.000s	72.472us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	19.000s	72.472us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	19.000s	72.472us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	18.000s	55.950us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	18.000s	55.950us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	16.000s	109.424us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_cipher_fi	45.000s	65.648ms	322	350	92.00
		aes_ctr_fi	11.000s	62.307us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	16.000s	109.424us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_cipher_fi	45.000s	65.648ms	322	350	92.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	45.000s	65.648ms	322	350	92.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	16.000s	109.424us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_ctr_fi	11.000s	62.307us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_cipher_fi	45.000s	65.648ms	322	350	92.00
		aes_ctr_fi	11.000s	62.307us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	21.000s	141.624us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_cipher_fi	45.000s	65.648ms	322	350	92.00
		aes_ctr_fi	11.000s	62.307us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_cipher_fi	45.000s	65.648ms	322	350	92.00
		aes_ctr_fi	11.000s	62.307us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_ctr_fi	11.000s	62.307us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	16.000s	109.424us	50	50	100.00
		aes_control_fi	52.000s	16.275ms	280	300	93.33
		aes_cipher_fi	45.000s	65.648ms	322	350	92.00
V2S		TOTAL			934	985	94.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.950m	5.588ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.39	94.09	98.83	93.77	97.64	91.11	98.85	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 36 failures:
- Test aes_cipher_fi has 18 failures.
  - 1.aes_cipher_fi.45482159549841258165913890539116997221285276252373794609985527689129703916779
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job ID: smart:59f9a267-5fe0-4355-ab9c-da37369db58d
```
  - 28.aes_cipher_fi.75645148887356343641158049869351575004445854130492478591884458154663648016961
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b6689f05-bc3a-4df7-a142-4b9e12c9aa16
```
  - ... and 16 more failures.
- Test aes_control_fi has 17 failures.
  - 13.aes_control_fi.750284082401449735412384932216275812922463100794178080715145336062034709898
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:d1ff4cbe-3706-48c7-86f7-5bcf0ff26c2c
```
  - 26.aes_control_fi.77784793169717443962587483513431786331899345231517183595464235992072304049913
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_control_fi/latest/run.log
```
  Job ID: smart:6e50dec1-c73a-4257-9df8-7d390b4107fd
```
  - ... and 15 more failures.
- Test aes_ctr_fi has 1 failures.
  - 43.aes_ctr_fi.71115270629649132983008482481849952700811394643805622985425402743567829331938
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_ctr_fi/latest/run.log
```
  Job ID: smart:79118653-f1d4-4596-b9e0-342c1d65b54f
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 22.aes_cipher_fi.3829849009185677961266698975960475112550191835902621625140833847035616571509
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10044752433 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10044752433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.aes_cipher_fi.69430678285286237597540221639513866646050750593736992165761381273653130370166
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/39.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003885794 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003885794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

3.aes_stress_all_with_rand_reset.63265388583825892692242295835527640008568411944431540488201036722847359937666
Line 1195, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9888974271 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9888974271 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.79148838830897152366932105995154513458072239873251449690058664349465914317876
Line 1163, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5588373048 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 5588373048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.64799440774866643864238430069276237189885004162074969635779002247150272952112
Line 1125, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 616488325 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 616488325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.47960478699105598685151853912177051383108525359726452125744416122340430024888
Line 1657, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 854025601 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 854025601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_control_fi has 3 failures.
  - 194.aes_control_fi.99479358839472707976025805436873136889907727488893921129788574011204748231888
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/194.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008051099 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008051099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 251.aes_control_fi.34193140355327850319377475638407384840413608614592202512426895153608120724954
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/251.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015253351 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015253351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 0.aes_core_fi.111546026053783894329100069373438557286810107415145699607817070972860620397660
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003192508 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003192508 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_core_fi.36152536300574990494275266987494192382164797679703205136259102173343358795220
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006912517 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006912517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_aliasing has 1 failures.
  - 1.aes_csr_aliasing.2117261825202424515714333937380688655734271643378649904733198670347506778480
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10058716868 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x18e1e684) == 0x0
  UVM_INFO @ 10058716868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.75877937479475027394386437378388511898908465502527119881692313243963298499909
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 786724833 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 786724833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```