AES/UNMASKED Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	84.971us	1	1	100.00
V1	smoke	aes_smoke	4.000s	57.650us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	61.702us	5	5	100.00
V1	csr_rw	aes_csr_rw	6.000s	76.791us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	182.454us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	246.426us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	135.661us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	6.000s	76.791us	20	20	100.00
		aes_csr_aliasing	5.000s	246.426us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	57.650us	50	50	100.00
		aes_config_error	5.000s	293.567us	50	50	100.00
		aes_stress	5.000s	287.676us	50	50	100.00
V2	key_length	aes_smoke	4.000s	57.650us	50	50	100.00
		aes_config_error	5.000s	293.567us	50	50	100.00
		aes_stress	5.000s	287.676us	50	50	100.00
V2	back2back	aes_stress	5.000s	287.676us	50	50	100.00
		aes_b2b	10.000s	441.150us	50	50	100.00
V2	backpressure	aes_stress	5.000s	287.676us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	57.650us	50	50	100.00
		aes_config_error	5.000s	293.567us	50	50	100.00
		aes_stress	5.000s	287.676us	50	50	100.00
		aes_alert_reset	5.000s	185.937us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	63.311us	50	50	100.00
		aes_config_error	5.000s	293.567us	50	50	100.00
		aes_alert_reset	5.000s	185.937us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	55.145us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	105.828us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	185.937us	50	50	100.00
V2	stress	aes_stress	5.000s	287.676us	50	50	100.00
V2	sideload	aes_stress	5.000s	287.676us	50	50	100.00
		aes_sideload	5.000s	144.362us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	264.810us	50	50	100.00
V2	stress_all	aes_stress_all	26.000s	1.150ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	91.595us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	126.179us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	126.179us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	61.702us	5	5	100.00
		aes_csr_rw	6.000s	76.791us	20	20	100.00
		aes_csr_aliasing	5.000s	246.426us	5	5	100.00
		aes_same_csr_outstanding	7.000s	91.537us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	61.702us	5	5	100.00
		aes_csr_rw	6.000s	76.791us	20	20	100.00
		aes_csr_aliasing	5.000s	246.426us	5	5	100.00
		aes_same_csr_outstanding	7.000s	91.537us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	5.000s	182.314us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_cipher_fi	48.000s	32.178ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	6.000s	188.166us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	6.000s	188.166us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	6.000s	188.166us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	6.000s	188.166us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	7.000s	144.292us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.856ms	5	5	100.00
		aes_tl_intg_err	7.000s	215.431us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	215.431us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	185.937us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	6.000s	188.166us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	57.650us	50	50	100.00
		aes_stress	5.000s	287.676us	50	50	100.00
		aes_alert_reset	5.000s	185.937us	50	50	100.00
		aes_core_fi	27.000s	10.022ms	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	6.000s	188.166us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	3.000s	106.190us	50	50	100.00
		aes_stress	5.000s	287.676us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	287.676us	50	50	100.00
		aes_sideload	5.000s	144.362us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	3.000s	106.190us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	3.000s	106.190us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	3.000s	106.190us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	3.000s	106.190us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	3.000s	106.190us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	287.676us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	287.676us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	608.653us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_cipher_fi	48.000s	32.178ms	323	350	92.29
		aes_ctr_fi	4.000s	125.456us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	608.653us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_cipher_fi	48.000s	32.178ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	32.178ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	608.653us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_ctr_fi	4.000s	125.456us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_cipher_fi	48.000s	32.178ms	323	350	92.29
		aes_ctr_fi	4.000s	125.456us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	185.937us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_cipher_fi	48.000s	32.178ms	323	350	92.29
		aes_ctr_fi	4.000s	125.456us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_cipher_fi	48.000s	32.178ms	323	350	92.29
		aes_ctr_fi	4.000s	125.456us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_ctr_fi	4.000s	125.456us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	608.653us	48	50	96.00
		aes_control_fi	50.000s	10.003ms	278	300	92.67
		aes_cipher_fi	48.000s	32.178ms	323	350	92.29
V2S		TOTAL			932	985	94.62
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.333m	5.486ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.25	97.55	94.48	98.81	93.74	97.72	93.33	98.85	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_control_fi has 13 failures.
  - 6.aes_control_fi.53540573036841364665663145360700406806154946852618633637389480185125668458508
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:76572e45-7eb2-4323-a330-796ea4f384f5
```
  - 10.aes_control_fi.7667345551163661875881742856032397482067347673472353294295540860750772771209
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:a7c0dd92-ae93-402b-ad97-7fc6e7b37f22
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 19 failures.
  - 37.aes_cipher_fi.59413977902809996998635943603525241996570312904251431508067545339499429654766
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  Job ID: smart:04362470-a916-4d94-afda-786b13f662cb
```
  - 74.aes_cipher_fi.2368874955860957022075831207842803477838418779566675818387310901551609315104
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/74.aes_cipher_fi/latest/run.log
```
  Job ID: smart:adff7b23-7ccc-4375-a3e8-5ee16f0859ea
```
  - ... and 17 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 17.aes_control_fi.61265527517272514561205082268655392955607430319073201991421605600941964581695
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012164999 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012164999 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.aes_control_fi.34747477127831879028090309084807619026507453096919664999549709051350793879448
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007605431 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007605431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.52882539189079421711994272907363993300915247569301553510174975174509775843546
Line 1082, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1221166875 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1221166875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.10958287303150431594351645544757095192691017965773786408061318760865508862048
Line 832, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 478603233 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 478603233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 9.aes_cipher_fi.76686833402397177129316089334666708982063702747867536168421237190832175244175
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002146324 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002146324 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_cipher_fi.72003147796237218366793871501928397587834361974043492363456622466308078950369
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011594253 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011594253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

2.aes_fi.17603930732942545233054245435902541667302536099540470599115711194641431153261
Line 1334, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 21294446 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 21274038 PS)
  UVM_ERROR @  21294446 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  21294446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aes_fi.83133790131469174027714242823629931960495742756384285121292358981479715012614
Line 4550, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 18547846 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 18537429 PS)
  UVM_ERROR @  18547846 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  18547846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.8089337798281059252754253536313717333272399100258027313147091861848782035231
    Line 1176, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 807475871 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 807475871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.70270598735235697493537804261751374455134862278447178902803648354095448760306
    Line 1495, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 392207804 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 392207804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 10.aes_core_fi.21999573830946307903364540903982551005195788721525599258413553407968297740517
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009337612 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009337612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 15.aes_core_fi.96613462552504945140019988432492835949995928404251692761415692292846880143555
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022285851 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022285851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```