AES/UNMASKED Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	5.000s	76.219us	1	1	100.00
V1	smoke	aes_smoke	16.000s	60.341us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	64.401us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	131.334us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	529.622us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	492.620us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	58.059us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	131.334us	20	20	100.00
		aes_csr_aliasing	5.000s	492.620us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	16.000s	60.341us	50	50	100.00
		aes_config_error	18.000s	54.796us	50	50	100.00
		aes_stress	15.000s	116.982us	50	50	100.00
V2	key_length	aes_smoke	16.000s	60.341us	50	50	100.00
		aes_config_error	18.000s	54.796us	50	50	100.00
		aes_stress	15.000s	116.982us	50	50	100.00
V2	back2back	aes_stress	15.000s	116.982us	50	50	100.00
		aes_b2b	19.000s	212.281us	50	50	100.00
V2	backpressure	aes_stress	15.000s	116.982us	50	50	100.00
V2	multi_message	aes_smoke	16.000s	60.341us	50	50	100.00
		aes_config_error	18.000s	54.796us	50	50	100.00
		aes_stress	15.000s	116.982us	50	50	100.00
		aes_alert_reset	24.000s	184.774us	49	50	98.00
V2	failure_test	aes_man_cfg_err	17.000s	74.364us	50	50	100.00
		aes_config_error	18.000s	54.796us	50	50	100.00
		aes_alert_reset	24.000s	184.774us	49	50	98.00
V2	trigger_clear_test	aes_clear	15.000s	190.540us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	770.910us	1	1	100.00
V2	reset_recovery	aes_alert_reset	24.000s	184.774us	49	50	98.00
V2	stress	aes_stress	15.000s	116.982us	50	50	100.00
V2	sideload	aes_stress	15.000s	116.982us	50	50	100.00
		aes_sideload	17.000s	72.626us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	629.888us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	3.619ms	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	127.119us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	338.652us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	338.652us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	64.401us	5	5	100.00
		aes_csr_rw	4.000s	131.334us	20	20	100.00
		aes_csr_aliasing	5.000s	492.620us	5	5	100.00
		aes_same_csr_outstanding	6.000s	330.719us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	64.401us	5	5	100.00
		aes_csr_rw	4.000s	131.334us	20	20	100.00
		aes_csr_aliasing	5.000s	492.620us	5	5	100.00
		aes_same_csr_outstanding	6.000s	330.719us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	25.000s	363.277us	50	50	100.00
V2S	fault_inject	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_cipher_fi	51.000s	16.449ms	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	64.844us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	64.844us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	64.844us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	64.844us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.267m	10.028ms	19	20	95.00
V2S	tl_intg_err	aes_sec_cm	16.000s	463.081us	5	5	100.00
		aes_tl_intg_err	6.000s	522.220us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	522.220us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	24.000s	184.774us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	64.844us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	16.000s	60.341us	50	50	100.00
		aes_stress	15.000s	116.982us	50	50	100.00
		aes_alert_reset	24.000s	184.774us	49	50	98.00
		aes_core_fi	1.100m	10.012ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	64.844us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	19.000s	91.448us	50	50	100.00
		aes_stress	15.000s	116.982us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	15.000s	116.982us	50	50	100.00
		aes_sideload	17.000s	72.626us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	19.000s	91.448us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	19.000s	91.448us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	19.000s	91.448us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	19.000s	91.448us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	19.000s	91.448us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	15.000s	116.982us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	15.000s	116.982us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	22.000s	125.694us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_cipher_fi	51.000s	16.449ms	319	350	91.14
		aes_ctr_fi	19.000s	88.210us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	22.000s	125.694us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_cipher_fi	51.000s	16.449ms	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	16.449ms	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	22.000s	125.694us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_ctr_fi	19.000s	88.210us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_cipher_fi	51.000s	16.449ms	319	350	91.14
		aes_ctr_fi	19.000s	88.210us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	24.000s	184.774us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_cipher_fi	51.000s	16.449ms	319	350	91.14
		aes_ctr_fi	19.000s	88.210us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_cipher_fi	51.000s	16.449ms	319	350	91.14
		aes_ctr_fi	19.000s	88.210us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_ctr_fi	19.000s	88.210us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	22.000s	125.694us	50	50	100.00
		aes_control_fi	50.000s	16.445ms	283	300	94.33
		aes_cipher_fi	51.000s	16.449ms	319	350	91.14
V2S		TOTAL			931	985	94.52
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.083m	34.863ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.27	97.59	94.56	98.81	93.77	97.72	93.33	98.66	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
- Test aes_control_fi has 10 failures.
  - 3.aes_control_fi.15145761995982468432246665274470507546749227949851321682696260591358759034671
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:e601fc84-b97a-4571-a75d-018e22c9832b
```
  - 10.aes_control_fi.32391034930878056867204025192956593776627019768693448756782379050420427786956
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:45fdf22c-d810-44f9-90b8-56bc272c63a9
```
  - ... and 8 more failures.
- Test aes_ctr_fi has 1 failures.
  - 4.aes_ctr_fi.1772115115108743607148009245535634970109308215709003689476979851040593963994
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_ctr_fi/latest/run.log
```
  Job ID: smart:434d35f0-0dd2-435e-b77a-8af817ed4f1c
```
- Test aes_cipher_fi has 22 failures.
  - 10.aes_cipher_fi.35616724116435157090772573605899523389373446291329171320926642149244729701084
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f3b57efa-dc5b-424b-8067-847d7d8f4ba1
```
  - 59.aes_cipher_fi.110228852917337708611092481443031906959780548869475387664698766317512283192035
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  Job ID: smart:726e9066-1acc-4466-90ff-eb75581f7972
```
  - ... and 20 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 19.aes_cipher_fi.15329897799081320240361315299945767385800725689417114303511198754400491798837
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011823335 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011823335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.aes_cipher_fi.108889184941263626029513326911857716167324606883011369894465112382777098325980
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006818016 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006818016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 87.aes_control_fi.92442102080921375817726980486374555088246949819046427268953644805504211297206
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/87.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003230522 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003230522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 155.aes_control_fi.88061201036147696765453861358220156402181524480520161485239240996087830287349
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/155.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005913587 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005913587 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.53216161968072308483418839643851064432397665680773045456572536014341093730749
Line 664, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 377138229 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 377138229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.91216020321448789448281392522215044524905479067133832281247097858168380000557
Line 1193, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1354703504 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1354703504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

4.aes_stress_all_with_rand_reset.97009760271271919336103241241498629435802513938260200181916335302916251101100
Line 1264, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6080889750 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6080889750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.88842999535790974342810592585968204882912979198929358747131366569996101465782
Line 850, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 800208383 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 800208383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 19.aes_core_fi.39289934036522106361450549420547818937355659721534763943254327827049296420026
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008594008 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008594008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 45.aes_core_fi.73628907565766848825746316934221246212296360801760544133671381984170334277469
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003492198 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003492198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 5.aes_csr_mem_rw_with_rand_reset.46151865622458899725078430843845225304057449367405446049097805951190471448388
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 213642158 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 213642158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_shadow_reg_errors_with_csr_rw has 1 failures.
  - 18.aes_shadow_reg_errors_with_csr_rw.52892510941053127078560728717027359695972468837423321331380277268168991009600
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_FATAL @ 10028445204 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xb4302184) == 0x0
  UVM_INFO @ 10028445204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 20.aes_core_fi.111660320497538565153070615673066904836691691751199518395903711241444797469514
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012053136 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012053136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 25.aes_alert_reset.48673247835060444319835988625795771641362227490981969404550793636808376915035
    Line 3531, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 9518253 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 9508152 PS)
  UVM_ERROR @   9518253 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   9518253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```