AES/UNMASKED Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	69.503us	1	1	100.00
V1	smoke	aes_smoke	9.000s	59.937us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	12.000s	84.088us	5	5	100.00
V1	csr_rw	aes_csr_rw	7.000s	82.062us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	530.947us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	85.325us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	72.662us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	7.000s	82.062us	20	20	100.00
		aes_csr_aliasing	8.000s	85.325us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	59.937us	50	50	100.00
		aes_config_error	9.000s	113.711us	50	50	100.00
		aes_stress	14.000s	224.507us	50	50	100.00
V2	key_length	aes_smoke	9.000s	59.937us	50	50	100.00
		aes_config_error	9.000s	113.711us	50	50	100.00
		aes_stress	14.000s	224.507us	50	50	100.00
V2	back2back	aes_stress	14.000s	224.507us	50	50	100.00
		aes_b2b	12.000s	493.363us	50	50	100.00
V2	backpressure	aes_stress	14.000s	224.507us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	59.937us	50	50	100.00
		aes_config_error	9.000s	113.711us	50	50	100.00
		aes_stress	14.000s	224.507us	50	50	100.00
		aes_alert_reset	13.000s	361.296us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	78.510us	50	50	100.00
		aes_config_error	9.000s	113.711us	50	50	100.00
		aes_alert_reset	13.000s	361.296us	50	50	100.00
V2	trigger_clear_test	aes_clear	10.000s	91.218us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	2.064ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	361.296us	50	50	100.00
V2	stress	aes_stress	14.000s	224.507us	50	50	100.00
V2	sideload	aes_stress	14.000s	224.507us	50	50	100.00
		aes_sideload	9.000s	101.783us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	200.943us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	1.244ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	50.515us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	15.000s	407.828us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	15.000s	407.828us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	12.000s	84.088us	5	5	100.00
		aes_csr_rw	7.000s	82.062us	20	20	100.00
		aes_csr_aliasing	8.000s	85.325us	5	5	100.00
		aes_same_csr_outstanding	5.000s	359.231us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	12.000s	84.088us	5	5	100.00
		aes_csr_rw	7.000s	82.062us	20	20	100.00
		aes_csr_aliasing	8.000s	85.325us	5	5	100.00
		aes_same_csr_outstanding	5.000s	359.231us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	23.000s	141.832us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_cipher_fi	48.000s	10.002ms	315	350	90.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	60.003us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	60.003us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	60.003us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	60.003us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	93.238us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.205ms	5	5	100.00
		aes_tl_intg_err	9.000s	197.674us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	197.674us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	361.296us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	60.003us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	59.937us	50	50	100.00
		aes_stress	14.000s	224.507us	50	50	100.00
		aes_alert_reset	13.000s	361.296us	50	50	100.00
		aes_core_fi	22.000s	10.014ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	60.003us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	78.904us	50	50	100.00
		aes_stress	14.000s	224.507us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	224.507us	50	50	100.00
		aes_sideload	9.000s	101.783us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	78.904us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	78.904us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	78.904us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	78.904us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	78.904us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	224.507us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	224.507us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	75.273us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_cipher_fi	48.000s	10.002ms	315	350	90.00
		aes_ctr_fi	8.000s	53.077us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	75.273us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_cipher_fi	48.000s	10.002ms	315	350	90.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.002ms	315	350	90.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	75.273us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_ctr_fi	8.000s	53.077us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_cipher_fi	48.000s	10.002ms	315	350	90.00
		aes_ctr_fi	8.000s	53.077us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	361.296us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_cipher_fi	48.000s	10.002ms	315	350	90.00
		aes_ctr_fi	8.000s	53.077us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_cipher_fi	48.000s	10.002ms	315	350	90.00
		aes_ctr_fi	8.000s	53.077us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_ctr_fi	8.000s	53.077us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	75.273us	50	50	100.00
		aes_control_fi	49.000s	200.000ms	276	300	92.00
		aes_cipher_fi	48.000s	10.002ms	315	350	90.00
V2S		TOTAL			922	985	93.60
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.350m	28.808ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1529	1602	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	97.46	94.26	98.77	93.65	97.72	90.37	98.85	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 40 failures:
- Test aes_cipher_fi has 23 failures.
  - 1.aes_cipher_fi.28468351477255929908835278443858218724479037734304199689965214235457092436313
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f1bb47c8-7ded-42d7-94ce-e1246234bf08
```
  - 4.aes_cipher_fi.57943154796617099794458288624154123115120198783533491401082282544190568964892
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:83b8a4db-68ae-4b4c-afc7-6ae5e4d51a9f
```
  - ... and 21 more failures.
- Test aes_ctr_fi has 1 failures.
  - 9.aes_ctr_fi.77834432777029564828356491610658230864423867563354505266875080319368583875845
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_ctr_fi/latest/run.log
```
  Job ID: smart:62ba74e0-b00c-457a-bde1-dee5b2f36849
```
- Test aes_control_fi has 16 failures.
  - 22.aes_control_fi.33781907805992804805795396507729263452635344266242725538953351564046794357844
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  Job ID: smart:11fcd739-6570-4880-9cda-480eaf8cb028
```
  - 38.aes_control_fi.16430434236118782264101942920592816166264571200294557861359201887666460144257
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_control_fi/latest/run.log
```
  Job ID: smart:95bbd2cf-cf45-4833-997d-4d8cebf77f15
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 19.aes_cipher_fi.99205044491625823640830590742891088278331450670559110552215144380510068845582
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10026101200 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026101200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.66613190507531063481838589255381891550335637917947591059917512982824489022198
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011903473 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011903473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.106680604252019276962673208827139331820447866449478790593227053485075937013124
Line 484, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 28807673714 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 28807673714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.93206562252273326187084468774690518160846536560144996474457598690779284864145
Line 624, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 133907429 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 133907429 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 27.aes_control_fi.71968887269207189892777773118809412626041924596054852818973539258026819407667
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008748902 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008748902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 35.aes_control_fi.35886352825587551364262906129424690938936456223316646265405914933160742933848
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003865866 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003865866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

5.aes_stress_all_with_rand_reset.101464123275264112824622513556981170416074424001880172588570317428877265984667
Line 797, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 161161218 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 161161218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.20890429159197164566128437789814476463327127927552778981654477813272591500753
Line 1260, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 332370181 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 332370181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 0.aes_core_fi.14159862926342394887628903562700323128540311641154091807214170177847388861606
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035250673 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035250673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.aes_core_fi.42665943383932295315668587419611940719343039246587179820853159787870863379235
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013799305 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013799305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 2.aes_core_fi.115675050130936381848263927446591086836945491737498351055722156081254419511787
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10091535537 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10091535537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 195.aes_control_fi.82340281399244985016537749436973138579352747823340125142163021450756271473738
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/195.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```