AES/UNMASKED Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	8.000s	76.599us	1	1	100.00
V1	smoke	aes_smoke	19.000s	241.917us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	60.487us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	58.798us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	184.368us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	130.280us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	224.444us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	58.798us	20	20	100.00
		aes_csr_aliasing	5.000s	130.280us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	19.000s	241.917us	50	50	100.00
		aes_config_error	14.000s	87.701us	50	50	100.00
		aes_stress	14.000s	119.126us	50	50	100.00
V2	key_length	aes_smoke	19.000s	241.917us	50	50	100.00
		aes_config_error	14.000s	87.701us	50	50	100.00
		aes_stress	14.000s	119.126us	50	50	100.00
V2	back2back	aes_stress	14.000s	119.126us	50	50	100.00
		aes_b2b	15.000s	285.577us	50	50	100.00
V2	backpressure	aes_stress	14.000s	119.126us	50	50	100.00
V2	multi_message	aes_smoke	19.000s	241.917us	50	50	100.00
		aes_config_error	14.000s	87.701us	50	50	100.00
		aes_stress	14.000s	119.126us	50	50	100.00
		aes_alert_reset	19.000s	173.738us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	120.998us	50	50	100.00
		aes_config_error	14.000s	87.701us	50	50	100.00
		aes_alert_reset	19.000s	173.738us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	81.133us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	407.678us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	173.738us	50	50	100.00
V2	stress	aes_stress	14.000s	119.126us	50	50	100.00
V2	sideload	aes_stress	14.000s	119.126us	50	50	100.00
		aes_sideload	13.000s	121.760us	50	50	100.00
V2	deinitialization	aes_deinit	11.000s	355.985us	50	50	100.00
V2	stress_all	aes_stress_all	25.000s	3.242ms	9	10	90.00
V2	alert_test	aes_alert_test	13.000s	56.936us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	2.410ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	2.410ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	60.487us	5	5	100.00
		aes_csr_rw	4.000s	58.798us	20	20	100.00
		aes_csr_aliasing	5.000s	130.280us	5	5	100.00
		aes_same_csr_outstanding	4.000s	352.026us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	60.487us	5	5	100.00
		aes_csr_rw	4.000s	58.798us	20	20	100.00
		aes_csr_aliasing	5.000s	130.280us	5	5	100.00
		aes_same_csr_outstanding	4.000s	352.026us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	12.000s	578.661us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_cipher_fi	49.000s	27.192ms	313	350	89.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	65.222us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	65.222us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	65.222us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	65.222us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	643.348us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	3.044ms	5	5	100.00
		aes_tl_intg_err	5.000s	306.592us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	306.592us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	173.738us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	65.222us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	19.000s	241.917us	50	50	100.00
		aes_stress	14.000s	119.126us	50	50	100.00
		aes_alert_reset	19.000s	173.738us	50	50	100.00
		aes_core_fi	1.700m	10.039ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	65.222us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	23.000s	71.018us	50	50	100.00
		aes_stress	14.000s	119.126us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	119.126us	50	50	100.00
		aes_sideload	13.000s	121.760us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	23.000s	71.018us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	23.000s	71.018us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	23.000s	71.018us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	23.000s	71.018us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	23.000s	71.018us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	119.126us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	119.126us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	94.283us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_cipher_fi	49.000s	27.192ms	313	350	89.43
		aes_ctr_fi	13.000s	86.926us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	94.283us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_cipher_fi	49.000s	27.192ms	313	350	89.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	27.192ms	313	350	89.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	94.283us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_ctr_fi	13.000s	86.926us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_cipher_fi	49.000s	27.192ms	313	350	89.43
		aes_ctr_fi	13.000s	86.926us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	173.738us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_cipher_fi	49.000s	27.192ms	313	350	89.43
		aes_ctr_fi	13.000s	86.926us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_cipher_fi	49.000s	27.192ms	313	350	89.43
		aes_ctr_fi	13.000s	86.926us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_ctr_fi	13.000s	86.926us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	94.283us	50	50	100.00
		aes_control_fi	50.000s	32.176ms	280	300	93.33
		aes_cipher_fi	49.000s	27.192ms	313	350	89.43
V2S		TOTAL			924	985	93.81
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.883m	10.057ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1529	1602	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.20	97.52	94.39	98.75	93.83	97.72	91.11	98.66	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 35 failures:
- Test aes_control_fi has 14 failures.
  - 10.aes_control_fi.21302735839458284201475411122703387816063710010212957624008138331364869164010
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job ID: smart:855879f8-5c5a-4e12-86ae-32f0189bbefd
```
  - 19.aes_control_fi.9229474166913032849949074154275099606671363959452159673807171360162886254877
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_control_fi/latest/run.log
```
  Job ID: smart:07b30f0a-b308-4b4f-98bb-520c960849cb
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 21 failures.
  - 13.aes_cipher_fi.2107871399089270574397956494256793676324459947922528301197632192653596536510
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_cipher_fi/latest/run.log
```
  Job ID: smart:59e4e9e8-fe21-424a-88ec-6b4740f65789
```
  - 24.aes_cipher_fi.7120863270691964188388436747473736324662067760968352329529810289230852148200
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job ID: smart:443705e9-f61c-436e-8f72-4568ba9854e0
```
  - ... and 19 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_cipher_fi has 16 failures.
  - 22.aes_cipher_fi.11231178892846247563928090114187627881674637853180573420829311945379595465811
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009386095 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009386095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_cipher_fi.31518665583944328802764058290010335712282808940502191707800262818635143603748
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005170391 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005170391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.23445846501992739661817145646860267109991405062090811857141073722642488728633
Line 1529, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3798573896 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3798573896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.48041399691320340131258054186586563090505968386716621486061119936915245397172
Line 807, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10056519680 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 10056519680 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_control_fi has 6 failures.
  - 0.aes_control_fi.49812976213782953474843756199937804213382038271970463911699721815704033482194
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016370257 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016370257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 97.aes_control_fi.30034108468687634398377937780838332668163142314541690268793491063712485046084
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/97.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008952886 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008952886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 1.aes_core_fi.20729782977473874620878816564185454928982593465051782781889753571638170101402
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003827263 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003827263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.aes_core_fi.88831972540194834600108489631305182997818466421830174154195351453924608875950
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003627295 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003627295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

1.aes_stress_all_with_rand_reset.10301303843951031742273915514987331766482246106561587533822618978528405429001
Line 1587, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2281107966 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2281107966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.114964125867020422523592454515801182565868127698513511323564091953353253561396
Line 1403, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1452121045 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1452121045 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.106791045238917099656031459737048758388558872198722626680944561518258831103518
    Line 6929, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 44519346 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 44509346 PS)
  UVM_ERROR @  44519346 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  44519346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 13.aes_csr_mem_rw_with_rand_reset.87917501816283286095825977532053253453052938908726167211815632761497245139567
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 224444462 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 224444462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 54.aes_core_fi.101916054003360933047138168902107307529915968016487852535466127206491677966734
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10038837309 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x69ea3684) == 0x0
  UVM_INFO @ 10038837309 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```