AES/UNMASKED Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: `2cf28c40e5`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	89.041us	1	1	100.00
V1	smoke	aes_smoke	10.000s	99.425us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	97.213us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	65.919us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	627.749us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	255.212us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	6.000s	210.676us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	65.919us	20	20	100.00
		aes_csr_aliasing	4.000s	255.212us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	10.000s	99.425us	50	50	100.00
		aes_config_error	5.000s	124.879us	50	50	100.00
		aes_stress	9.000s	461.783us	50	50	100.00
V2	key_length	aes_smoke	10.000s	99.425us	50	50	100.00
		aes_config_error	5.000s	124.879us	50	50	100.00
		aes_stress	9.000s	461.783us	50	50	100.00
V2	back2back	aes_stress	9.000s	461.783us	50	50	100.00
		aes_b2b	15.000s	125.561us	50	50	100.00
V2	backpressure	aes_stress	9.000s	461.783us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	99.425us	50	50	100.00
		aes_config_error	5.000s	124.879us	50	50	100.00
		aes_stress	9.000s	461.783us	50	50	100.00
		aes_alert_reset	8.000s	65.354us	49	50	98.00
V2	failure_test	aes_man_cfg_err	8.000s	52.514us	50	50	100.00
		aes_config_error	5.000s	124.879us	50	50	100.00
		aes_alert_reset	8.000s	65.354us	49	50	98.00
V2	trigger_clear_test	aes_clear	16.000s	202.792us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	9.000s	442.641us	1	1	100.00
V2	reset_recovery	aes_alert_reset	8.000s	65.354us	49	50	98.00
V2	stress	aes_stress	9.000s	461.783us	50	50	100.00
V2	sideload	aes_stress	9.000s	461.783us	50	50	100.00
		aes_sideload	10.000s	184.184us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	131.067us	50	50	100.00
V2	stress_all	aes_stress_all	35.000s	6.111ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	97.440us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	181.552us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	181.552us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	97.213us	5	5	100.00
		aes_csr_rw	3.000s	65.919us	20	20	100.00
		aes_csr_aliasing	4.000s	255.212us	5	5	100.00
		aes_same_csr_outstanding	4.000s	139.744us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	97.213us	5	5	100.00
		aes_csr_rw	3.000s	65.919us	20	20	100.00
		aes_csr_aliasing	4.000s	255.212us	5	5	100.00
		aes_same_csr_outstanding	4.000s	139.744us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	9.000s	240.921us	50	50	100.00
V2S	fault_inject	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_cipher_fi	49.000s	65.655ms	329	350	94.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	101.664us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	101.664us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	101.664us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	101.664us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	87.185us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.581ms	5	5	100.00
		aes_tl_intg_err	9.000s	190.128us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	190.128us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	8.000s	65.354us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	101.664us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	99.425us	50	50	100.00
		aes_stress	9.000s	461.783us	50	50	100.00
		aes_alert_reset	8.000s	65.354us	49	50	98.00
		aes_core_fi	44.000s	10.002ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	101.664us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	52.335us	50	50	100.00
		aes_stress	9.000s	461.783us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	461.783us	50	50	100.00
		aes_sideload	10.000s	184.184us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	52.335us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	52.335us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	52.335us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	52.335us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	52.335us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	461.783us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	461.783us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	8.000s	63.619us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_cipher_fi	49.000s	65.655ms	329	350	94.00
		aes_ctr_fi	18.000s	79.136us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	8.000s	63.619us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_cipher_fi	49.000s	65.655ms	329	350	94.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	65.655ms	329	350	94.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	8.000s	63.619us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_ctr_fi	18.000s	79.136us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_cipher_fi	49.000s	65.655ms	329	350	94.00
		aes_ctr_fi	18.000s	79.136us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	8.000s	65.354us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_cipher_fi	49.000s	65.655ms	329	350	94.00
		aes_ctr_fi	18.000s	79.136us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_cipher_fi	49.000s	65.655ms	329	350	94.00
		aes_ctr_fi	18.000s	79.136us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_ctr_fi	18.000s	79.136us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	8.000s	63.619us	48	50	96.00
		aes_control_fi	49.000s	10.002ms	278	300	92.67
		aes_cipher_fi	49.000s	65.655ms	329	350	94.00
V2S		TOTAL			935	985	94.92
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.933m	15.198ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1540	1602	96.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.50	94.35	98.81	93.63	97.64	93.33	98.85	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 22 failures:
- Test aes_control_fi has 14 failures.
  - 15.aes_control_fi.110127872725696548347025312946431324168978024413518035838679923400425334106000
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:bca6bce2-ce4f-416e-b3cb-64b1fdb0c5bc
```
  - 35.aes_control_fi.63490972213371657315207703142650139376283034388093772042467673082273336429659
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  Job ID: smart:b6a03aee-7407-416e-b704-ff6c853ee1c7
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 8 failures.
  - 46.aes_cipher_fi.58783180905632848329103713771533071126505066331208570695546873657852233421209
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_cipher_fi/latest/run.log
```
  Job ID: smart:89c4de51-e2b1-47e9-aea8-5e32d32c2164
```
  - 138.aes_cipher_fi.75106109577591387654902525120101950099760272705023185215607879825046656667197
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/138.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3d3c885c-4058-40f5-815a-0933135976bd
```
  - ... and 6 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 13 failures:
- Test aes_cipher_fi has 13 failures.
  - 33.aes_cipher_fi.114541444588705819406978998295239439286164928183797617922675928272700772869586
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008273383 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008273383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_cipher_fi.107195557986632267168935546096699995294001034153524780436222666102332531391378
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002937749 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002937749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 37.aes_control_fi.42835513450133763966619478270310341038901011323347035176432832691356273047707
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020650626 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020650626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_control_fi.32176174311256595600646952391418969568403617230740018664307478170850058224991
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005884399 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005884399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.85048870263702952602935641076247589663504419378015355661688517659320709888521
Line 1135, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 9328208498 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 9328208498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.8448794184580814686906493958157215322150461660508354011041199041843292851558
Line 1157, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3070002442 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3070002442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

3.aes_stress_all_with_rand_reset.45703870646188958045906983618452712838913953281284055964743660200847291016113
Line 729, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 617222565 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 617222565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.60300171451646672241462334763329021742135160598374152968170281623096031698828
Line 609, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1894998878 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1894998878 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 17.aes_core_fi.20190945149076052727283502419094866189640043565572393234187533181489076862265
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002110403 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002110403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_core_fi.107577414443837456207409044452109062517170344151416623594570134433902663623665
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003309739 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003309739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 1.aes_core_fi.113643729813565488006177714329955117328639885031106417517500094447392313864636
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10029777669 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029777669 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 48.aes_core_fi.28634432443756964110676580540658591666453988902732180641753641418629186095724
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022500333 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022500333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

19.aes_fi.66976408449378860453393879829785669881794531862816691012115548084111449835220
Line 9981, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_fi/latest/run.log

  UVM_FATAL @ 101317955 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 101317955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.aes_fi.65725377894120184567179426817184085317282037573405576130434909846592336376307
Line 3548, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_fi/latest/run.log

  UVM_FATAL @  21958965 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  21958965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:830) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 15.aes_csr_mem_rw_with_rand_reset.100573686878595153948332036521617024948349271764500973711713318650311132124880
    Line 292, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 210676315 ps: (cip_base_vseq.sv:830) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 210676315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 22.aes_alert_reset.10080009445639522954002380651500804957871594098501334902424707001951888958231
    Line 1352, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 48558487 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 48518487 PS)
  UVM_ERROR @  48558487 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  48558487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```