AES/UNMASKED Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 3.000s 74.293us 1 1 100.00
V1 smoke aes_smoke 9.000s 187.133us 50 50 100.00
V1 csr_hw_reset aes_csr_hw_reset 3.000s 70.089us 5 5 100.00
V1 csr_rw aes_csr_rw 3.000s 53.145us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 10.000s 840.851us 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 248.943us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 4.000s 69.469us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 3.000s 53.145us 20 20 100.00
aes_csr_aliasing 5.000s 248.943us 5 5 100.00
V1 TOTAL 106 106 100.00
V2 algorithm aes_smoke 9.000s 187.133us 50 50 100.00
aes_config_error 13.000s 81.015us 50 50 100.00
aes_stress 9.000s 100.120us 50 50 100.00
V2 key_length aes_smoke 9.000s 187.133us 50 50 100.00
aes_config_error 13.000s 81.015us 50 50 100.00
aes_stress 9.000s 100.120us 50 50 100.00
V2 back2back aes_stress 9.000s 100.120us 50 50 100.00
aes_b2b 12.000s 333.033us 50 50 100.00
V2 backpressure aes_stress 9.000s 100.120us 50 50 100.00
V2 multi_message aes_smoke 9.000s 187.133us 50 50 100.00
aes_config_error 13.000s 81.015us 50 50 100.00
aes_stress 9.000s 100.120us 50 50 100.00
aes_alert_reset 14.000s 99.745us 50 50 100.00
V2 failure_test aes_man_cfg_err 13.000s 61.811us 50 50 100.00
aes_config_error 13.000s 81.015us 50 50 100.00
aes_alert_reset 14.000s 99.745us 50 50 100.00
V2 trigger_clear_test aes_clear 9.000s 120.132us 50 50 100.00
V2 nist_test_vectors aes_nist_vectors 6.000s 174.348us 1 1 100.00
V2 reset_recovery aes_alert_reset 14.000s 99.745us 50 50 100.00
V2 stress aes_stress 9.000s 100.120us 50 50 100.00
V2 sideload aes_stress 9.000s 100.120us 50 50 100.00
aes_sideload 9.000s 112.540us 50 50 100.00
V2 deinitialization aes_deinit 9.000s 290.408us 50 50 100.00
V2 stress_all aes_stress_all 36.000s 2.424ms 10 10 100.00
V2 alert_test aes_alert_test 8.000s 61.856us 50 50 100.00
V2 tl_d_oob_addr_access aes_tl_errors 6.000s 380.512us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 6.000s 380.512us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 3.000s 70.089us 5 5 100.00
aes_csr_rw 3.000s 53.145us 20 20 100.00
aes_csr_aliasing 5.000s 248.943us 5 5 100.00
aes_same_csr_outstanding 4.000s 110.453us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 3.000s 70.089us 5 5 100.00
aes_csr_rw 3.000s 53.145us 20 20 100.00
aes_csr_aliasing 5.000s 248.943us 5 5 100.00
aes_same_csr_outstanding 4.000s 110.453us 20 20 100.00
V2 TOTAL 501 501 100.00
V2S reseeding aes_reseed 10.000s 88.179us 49 50 98.00
V2S fault_inject aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_cipher_fi 50.000s 31.529ms 331 350 94.57
V2S shadow_reg_update_error aes_shadow_reg_errors 4.000s 276.270us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 4.000s 276.270us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 4.000s 276.270us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 4.000s 276.270us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 8.000s 84.450us 20 20 100.00
V2S tl_intg_err aes_sec_cm 9.000s 1.646ms 5 5 100.00
aes_tl_intg_err 5.000s 961.763us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 5.000s 961.763us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 14.000s 99.745us 50 50 100.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 4.000s 276.270us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 9.000s 187.133us 50 50 100.00
aes_stress 9.000s 100.120us 50 50 100.00
aes_alert_reset 14.000s 99.745us 50 50 100.00
aes_core_fi 1.750m 10.043ms 66 70 94.29
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 4.000s 276.270us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 11.000s 64.434us 50 50 100.00
aes_stress 9.000s 100.120us 50 50 100.00
V2S sec_cm_key_sideload aes_stress 9.000s 100.120us 50 50 100.00
aes_sideload 9.000s 112.540us 50 50 100.00
V2S sec_cm_key_sw_unreadable aes_readability 11.000s 64.434us 50 50 100.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 11.000s 64.434us 50 50 100.00
V2S sec_cm_key_sec_wipe aes_readability 11.000s 64.434us 50 50 100.00
V2S sec_cm_iv_config_sec_wipe aes_readability 11.000s 64.434us 50 50 100.00
V2S sec_cm_data_reg_sec_wipe aes_readability 11.000s 64.434us 50 50 100.00
V2S sec_cm_data_reg_key_sca aes_stress 9.000s 100.120us 50 50 100.00
V2S sec_cm_key_masking aes_stress 9.000s 100.120us 50 50 100.00
V2S sec_cm_main_fsm_sparse aes_fi 14.000s 148.001us 50 50 100.00
V2S sec_cm_main_fsm_redun aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_cipher_fi 50.000s 31.529ms 331 350 94.57
aes_ctr_fi 8.000s 97.327us 50 50 100.00
V2S sec_cm_cipher_fsm_sparse aes_fi 14.000s 148.001us 50 50 100.00
V2S sec_cm_cipher_fsm_redun aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_cipher_fi 50.000s 31.529ms 331 350 94.57
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 50.000s 31.529ms 331 350 94.57
V2S sec_cm_ctr_fsm_sparse aes_fi 14.000s 148.001us 50 50 100.00
V2S sec_cm_ctr_fsm_redun aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_ctr_fi 8.000s 97.327us 50 50 100.00
V2S sec_cm_ctrl_sparse aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_cipher_fi 50.000s 31.529ms 331 350 94.57
aes_ctr_fi 8.000s 97.327us 50 50 100.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 14.000s 99.745us 50 50 100.00
V2S sec_cm_main_fsm_local_esc aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_cipher_fi 50.000s 31.529ms 331 350 94.57
aes_ctr_fi 8.000s 97.327us 50 50 100.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_cipher_fi 50.000s 31.529ms 331 350 94.57
aes_ctr_fi 8.000s 97.327us 50 50 100.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_ctr_fi 8.000s 97.327us 50 50 100.00
V2S sec_cm_data_reg_local_esc aes_fi 14.000s 148.001us 50 50 100.00
aes_control_fi 48.000s 10.003ms 273 300 91.00
aes_cipher_fi 50.000s 31.529ms 331 350 94.57
V2S TOTAL 934 985 94.82
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 3.900m 10.767ms 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 1541 1602 96.19

Testplan Progress

Items Total Written Passing Progress
V1 7 7 7 100.00
V2 13 13 13 100.00
V2S 11 11 7 63.64
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.17 97.50 94.35 98.75 93.65 97.72 91.11 98.85 96.61

Failure Buckets

Past Results