AES/UNMASKED Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: `0e5093d709`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	74.293us	1	1	100.00
V1	smoke	aes_smoke	9.000s	187.133us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	70.089us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	53.145us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	840.851us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	248.943us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	69.469us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	53.145us	20	20	100.00
		aes_csr_aliasing	5.000s	248.943us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	9.000s	187.133us	50	50	100.00
		aes_config_error	13.000s	81.015us	50	50	100.00
		aes_stress	9.000s	100.120us	50	50	100.00
V2	key_length	aes_smoke	9.000s	187.133us	50	50	100.00
		aes_config_error	13.000s	81.015us	50	50	100.00
		aes_stress	9.000s	100.120us	50	50	100.00
V2	back2back	aes_stress	9.000s	100.120us	50	50	100.00
		aes_b2b	12.000s	333.033us	50	50	100.00
V2	backpressure	aes_stress	9.000s	100.120us	50	50	100.00
V2	multi_message	aes_smoke	9.000s	187.133us	50	50	100.00
		aes_config_error	13.000s	81.015us	50	50	100.00
		aes_stress	9.000s	100.120us	50	50	100.00
		aes_alert_reset	14.000s	99.745us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	61.811us	50	50	100.00
		aes_config_error	13.000s	81.015us	50	50	100.00
		aes_alert_reset	14.000s	99.745us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	120.132us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	174.348us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	99.745us	50	50	100.00
V2	stress	aes_stress	9.000s	100.120us	50	50	100.00
V2	sideload	aes_stress	9.000s	100.120us	50	50	100.00
		aes_sideload	9.000s	112.540us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	290.408us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	2.424ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	61.856us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	380.512us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	380.512us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	70.089us	5	5	100.00
		aes_csr_rw	3.000s	53.145us	20	20	100.00
		aes_csr_aliasing	5.000s	248.943us	5	5	100.00
		aes_same_csr_outstanding	4.000s	110.453us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	70.089us	5	5	100.00
		aes_csr_rw	3.000s	53.145us	20	20	100.00
		aes_csr_aliasing	5.000s	248.943us	5	5	100.00
		aes_same_csr_outstanding	4.000s	110.453us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	88.179us	49	50	98.00
V2S	fault_inject	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_cipher_fi	50.000s	31.529ms	331	350	94.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	276.270us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	276.270us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	276.270us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	276.270us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	84.450us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	9.000s	1.646ms	5	5	100.00
		aes_tl_intg_err	5.000s	961.763us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	961.763us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	99.745us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	276.270us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	9.000s	187.133us	50	50	100.00
		aes_stress	9.000s	100.120us	50	50	100.00
		aes_alert_reset	14.000s	99.745us	50	50	100.00
		aes_core_fi	1.750m	10.043ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	276.270us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	11.000s	64.434us	50	50	100.00
		aes_stress	9.000s	100.120us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	100.120us	50	50	100.00
		aes_sideload	9.000s	112.540us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	11.000s	64.434us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	11.000s	64.434us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	11.000s	64.434us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	11.000s	64.434us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	11.000s	64.434us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	100.120us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	100.120us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	148.001us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_cipher_fi	50.000s	31.529ms	331	350	94.57
		aes_ctr_fi	8.000s	97.327us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	148.001us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_cipher_fi	50.000s	31.529ms	331	350	94.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	31.529ms	331	350	94.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	148.001us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_ctr_fi	8.000s	97.327us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_cipher_fi	50.000s	31.529ms	331	350	94.57
		aes_ctr_fi	8.000s	97.327us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	99.745us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_cipher_fi	50.000s	31.529ms	331	350	94.57
		aes_ctr_fi	8.000s	97.327us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_cipher_fi	50.000s	31.529ms	331	350	94.57
		aes_ctr_fi	8.000s	97.327us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_ctr_fi	8.000s	97.327us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	148.001us	50	50	100.00
		aes_control_fi	48.000s	10.003ms	273	300	91.00
		aes_cipher_fi	50.000s	31.529ms	331	350	94.57
V2S		TOTAL			934	985	94.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.900m	10.767ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1541	1602	96.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.50	94.35	98.75	93.65	97.72	91.11	98.85	96.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 17 failures.
  - 0.aes_control_fi.72980828014331590768776099674306333930887166686593512716417872277897160304214
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:e853f078-4bbb-40a9-8f84-9b6a4b8dec7c
```
  - 49.aes_control_fi.23626354049214835499615544395888890066653739125662317702945098755714163986864
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  Job ID: smart:221e6d3d-02c2-472c-8063-3eb51ad1cb7e
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 13 failures.
  - 40.aes_cipher_fi.65439067628753407870860916759525385801430697522639221884500228434356473420464
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f52648a6-88b8-42a1-97f8-eed429afe286
```
  - 66.aes_cipher_fi.41981744064055912198324046000997329907363968023041633180666813837954422805733
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/66.aes_cipher_fi/latest/run.log
```
  Job ID: smart:019a41ad-408e-4150-be11-cfb78becc9ad
```
  - ... and 11 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 30.aes_control_fi.62878927202267658285163088902794320670756638215525205079982209477245928319350
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008731646 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008731646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 64.aes_control_fi.217162826088967121088657835548619563668244380664881174446064589021156300743
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/64.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005664334 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005664334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 6 failures:
- Test aes_cipher_fi has 6 failures.
  - 104.aes_cipher_fi.38022426692606730479621837283334869788636171784354534398594224040412626063060
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/104.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012451915 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012451915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 145.aes_cipher_fi.39909912037755516166186557276749484191989350458610534949180720884867933193724
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/145.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007130933 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007130933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.76554342869392315069502562879231729910456670571215209457862691638595092200398
Line 1103, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1060878066 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1060878066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.19562656942684754782201925595997360855255619169734220043867463833586447384935
Line 449, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15375022854 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 15375022854 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

2.aes_stress_all_with_rand_reset.9607112093070170312013157499919424000817379794078524940312943044609411579728
Line 1442, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 635032761 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 635032761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.33814812785063235003943186663662262623692043345869802747093188789045863423032
Line 1078, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1145056612 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1145056612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 2.aes_core_fi.113065835448727211046955632242799179008167943736679445032018769729728808580718
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009425505 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009425505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.aes_core_fi.80005209500504748570860241057873872389831982816704877495887912128636989298836
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018775516 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018775516 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 18.aes_core_fi.72160596024429961107192492064433868150029814642751010383836425771476429885778
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10043025282 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xf0de9d84) == 0x0
  UVM_INFO @ 10043025282 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 36.aes_reseed.81941657328592046071635677910564454539194328498959076846255299722612767064051
    Line 410, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_reseed/latest/run.log
```
  UVM_FATAL @  69651156 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  69651156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```