AES/UNMASKED Simulation Results

Tuesday May 21 2024 19:02:35 UTC

GitHub Revision: `be3d980075`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85829748320245376283659198434338498577935164172956485671224275001047693479661

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	89.663us	1	1	100.00
V1	smoke	aes_smoke	18.000s	83.408us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	62.060us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	60.349us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	179.405us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	875.170us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	7.000s	124.883us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	60.349us	20	20	100.00
		aes_csr_aliasing	7.000s	875.170us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	18.000s	83.408us	50	50	100.00
		aes_config_error	9.000s	124.380us	50	50	100.00
		aes_stress	14.000s	75.909us	50	50	100.00
V2	key_length	aes_smoke	18.000s	83.408us	50	50	100.00
		aes_config_error	9.000s	124.380us	50	50	100.00
		aes_stress	14.000s	75.909us	50	50	100.00
V2	back2back	aes_stress	14.000s	75.909us	50	50	100.00
		aes_b2b	14.000s	175.032us	50	50	100.00
V2	backpressure	aes_stress	14.000s	75.909us	50	50	100.00
V2	multi_message	aes_smoke	18.000s	83.408us	50	50	100.00
		aes_config_error	9.000s	124.380us	50	50	100.00
		aes_stress	14.000s	75.909us	50	50	100.00
		aes_alert_reset	9.000s	143.944us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	58.920us	50	50	100.00
		aes_config_error	9.000s	124.380us	50	50	100.00
		aes_alert_reset	9.000s	143.944us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	179.568us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	122.192us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	143.944us	50	50	100.00
V2	stress	aes_stress	14.000s	75.909us	50	50	100.00
V2	sideload	aes_stress	14.000s	75.909us	50	50	100.00
		aes_sideload	13.000s	62.366us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	118.481us	50	50	100.00
V2	stress_all	aes_stress_all	29.000s	3.976ms	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	98.928us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	792.321us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	792.321us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	62.060us	5	5	100.00
		aes_csr_rw	8.000s	60.349us	20	20	100.00
		aes_csr_aliasing	7.000s	875.170us	5	5	100.00
		aes_same_csr_outstanding	4.000s	305.637us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	62.060us	5	5	100.00
		aes_csr_rw	8.000s	60.349us	20	20	100.00
		aes_csr_aliasing	7.000s	875.170us	5	5	100.00
		aes_same_csr_outstanding	4.000s	305.637us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	11.000s	1.108ms	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_cipher_fi	49.000s	16.441ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	65.078us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	65.078us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	65.078us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	65.078us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	103.788us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	529.860us	5	5	100.00
		aes_tl_intg_err	6.000s	464.754us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	464.754us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	143.944us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	65.078us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	18.000s	83.408us	50	50	100.00
		aes_stress	14.000s	75.909us	50	50	100.00
		aes_alert_reset	9.000s	143.944us	50	50	100.00
		aes_core_fi	58.000s	10.014ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	65.078us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	18.000s	64.598us	50	50	100.00
		aes_stress	14.000s	75.909us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	75.909us	50	50	100.00
		aes_sideload	13.000s	62.366us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	18.000s	64.598us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	18.000s	64.598us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	18.000s	64.598us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	18.000s	64.598us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	18.000s	64.598us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	75.909us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	75.909us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	214.362us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_cipher_fi	49.000s	16.441ms	325	350	92.86
		aes_ctr_fi	8.000s	64.258us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	214.362us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_cipher_fi	49.000s	16.441ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	16.441ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	214.362us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_ctr_fi	8.000s	64.258us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_cipher_fi	49.000s	16.441ms	325	350	92.86
		aes_ctr_fi	8.000s	64.258us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	143.944us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_cipher_fi	49.000s	16.441ms	325	350	92.86
		aes_ctr_fi	8.000s	64.258us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_cipher_fi	49.000s	16.441ms	325	350	92.86
		aes_ctr_fi	8.000s	64.258us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_ctr_fi	8.000s	64.258us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	214.362us	50	50	100.00
		aes_control_fi	51.000s	10.003ms	282	300	94.00
		aes_cipher_fi	49.000s	16.441ms	325	350	92.86
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	58.000s	2.717ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1543	1602	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.54	94.43	98.81	93.60	97.64	93.33	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 27 failures:
- Test aes_cipher_fi has 17 failures.
  - 3.aes_cipher_fi.98750660337158715028294285763349454970056090729588800598648423303176968896389
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3e676e96-3768-4775-8414-799357d4e42a
```
  - 9.aes_cipher_fi.47606610484797291436135742768443017824123125774059717607891384087988762519108
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3d51b3e2-dac3-4124-a50f-51a4399689d3
```
  - ... and 15 more failures.
- Test aes_ctr_fi has 1 failures.
  - 36.aes_ctr_fi.1315415759232910518283280346812762048854288056022396818581059328608119998925
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_ctr_fi/latest/run.log
```
  Job ID: smart:5c4a9001-8b3d-42d7-a66a-91660afab47d
```
- Test aes_control_fi has 9 failures.
  - 49.aes_control_fi.92216677034781884544889990950666358793149593008660163865204473340021133907849
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  Job ID: smart:ba479064-8b63-4299-8e63-a335fc83c435
```
  - 74.aes_control_fi.15392101050875813125141388820851643771238242520457927031123743958295336933266
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/74.aes_control_fi/latest/run.log
```
  Job ID: smart:ddfbfda2-e85d-4b9f-8215-03dd96ff5ffe
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 2.aes_control_fi.6279704594907589429399332299714217406117367087485131310773386647707947352513
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006061883 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006061883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.aes_control_fi.33169177663575484912263655339778443148487921244301631987312773766234002009290
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012722998 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012722998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 97.aes_cipher_fi.100528074487276388156257136407906406627275290152202309899000063124608450491020
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/97.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010105125 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010105125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 100.aes_cipher_fi.65451524966790050289862923892868530565447091786546534760461440345467977164780
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/100.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007074614 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007074614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

1.aes_stress_all_with_rand_reset.30562948776737193876573857525254825277298803024470459491410901552011156818882
Line 747, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2716508024 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2716508024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.4167885984931701699106417104230678885707476352915105377908602507984963720247
Line 1972, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7358777898 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 7358777898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 4.aes_core_fi.86564149596319979362099091974462709922166440213913888326347072068247301029649
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009564633 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009564633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.aes_core_fi.85744987531367155688006565762073075051422888285331801037990020203997224987651
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009157658 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009157658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 0.aes_stress_all_with_rand_reset.28879035469183249422405281438419695590646571786844924944093852507707064033937
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  40984916 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  40984916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_stress_all_with_rand_reset.11288530855252519454620683275372951608401240081513424482596811901294633988850
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 187179314 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 187179314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.8905764369167861631674458284608474744664222882704513312648134101602247788893
    Line 1520, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2987659709 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2987659709 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 10.aes_core_fi.84374807304758541334679827776872444686210657117775814784045457485073448898221
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014263876 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014263876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```