AES/UNMASKED Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: `1579f6a912`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	92.494us	1	1	100.00
V1	smoke	aes_smoke	4.000s	72.536us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	147.716us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	97.923us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	995.007us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	433.288us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	74.827us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	97.923us	20	20	100.00
		aes_csr_aliasing	5.000s	433.288us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	72.536us	50	50	100.00
		aes_config_error	8.000s	65.560us	50	50	100.00
		aes_stress	5.000s	95.703us	50	50	100.00
V2	key_length	aes_smoke	4.000s	72.536us	50	50	100.00
		aes_config_error	8.000s	65.560us	50	50	100.00
		aes_stress	5.000s	95.703us	50	50	100.00
V2	back2back	aes_stress	5.000s	95.703us	50	50	100.00
		aes_b2b	14.000s	387.436us	50	50	100.00
V2	backpressure	aes_stress	5.000s	95.703us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	72.536us	50	50	100.00
		aes_config_error	8.000s	65.560us	50	50	100.00
		aes_stress	5.000s	95.703us	50	50	100.00
		aes_alert_reset	5.000s	136.204us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	64.440us	50	50	100.00
		aes_config_error	8.000s	65.560us	50	50	100.00
		aes_alert_reset	5.000s	136.204us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	119.600us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	232.317us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	136.204us	50	50	100.00
V2	stress	aes_stress	5.000s	95.703us	50	50	100.00
V2	sideload	aes_stress	5.000s	95.703us	50	50	100.00
		aes_sideload	5.000s	106.110us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	255.394us	50	50	100.00
V2	stress_all	aes_stress_all	24.000s	870.082us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	124.477us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	313.114us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	313.114us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	147.716us	5	5	100.00
		aes_csr_rw	3.000s	97.923us	20	20	100.00
		aes_csr_aliasing	5.000s	433.288us	5	5	100.00
		aes_same_csr_outstanding	4.000s	64.817us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	147.716us	5	5	100.00
		aes_csr_rw	3.000s	97.923us	20	20	100.00
		aes_csr_aliasing	5.000s	433.288us	5	5	100.00
		aes_same_csr_outstanding	4.000s	64.817us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	6.000s	478.908us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_cipher_fi	52.000s	121.161ms	327	350	93.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	146.313us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	146.313us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	146.313us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	146.313us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	85.546us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	614.156us	5	5	100.00
		aes_tl_intg_err	5.000s	328.992us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	328.992us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	136.204us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	146.313us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	72.536us	50	50	100.00
		aes_stress	5.000s	95.703us	50	50	100.00
		aes_alert_reset	5.000s	136.204us	50	50	100.00
		aes_core_fi	36.000s	10.005ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	146.313us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	65.878us	50	50	100.00
		aes_stress	5.000s	95.703us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	95.703us	50	50	100.00
		aes_sideload	5.000s	106.110us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	65.878us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	65.878us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	65.878us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	65.878us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	65.878us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	95.703us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	95.703us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	254.721us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_cipher_fi	52.000s	121.161ms	327	350	93.43
		aes_ctr_fi	5.000s	53.958us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	254.721us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_cipher_fi	52.000s	121.161ms	327	350	93.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	121.161ms	327	350	93.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	254.721us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_ctr_fi	5.000s	53.958us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_cipher_fi	52.000s	121.161ms	327	350	93.43
		aes_ctr_fi	5.000s	53.958us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	136.204us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_cipher_fi	52.000s	121.161ms	327	350	93.43
		aes_ctr_fi	5.000s	53.958us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_cipher_fi	52.000s	121.161ms	327	350	93.43
		aes_ctr_fi	5.000s	53.958us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_ctr_fi	5.000s	53.958us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	254.721us	50	50	100.00
		aes_control_fi	46.000s	15.784ms	265	300	88.33
		aes_cipher_fi	52.000s	121.161ms	327	350	93.43
V2S		TOTAL			923	985	93.71
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.350m	5.198ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1530	1602	95.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.27	97.57	94.52	98.81	93.83	97.72	93.33	98.85	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 32 failures:
- Test aes_control_fi has 19 failures.
  - 0.aes_control_fi.35028727486196264275144552897608474236824524140681860847960739726444669051010
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  Job ID: smart:e89268d1-d5f2-4917-bc84-33973e6d21c2
```
  - 8.aes_control_fi.83424265379581389167961643176649501712487361553231492374542057751716579136743
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job ID: smart:8367b97a-4b73-4b47-a54f-76b04bf70009
```
  - ... and 17 more failures.
- Test aes_cipher_fi has 12 failures.
  - 2.aes_cipher_fi.72963984398081579772182643918336607134461527859173645919592552378452686459212
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ced9f3dd-3d05-46d4-845c-26fe8b9d01ab
```
  - 22.aes_cipher_fi.59074641840653381020345797474666318262484563966765076786136708496164760051590
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_cipher_fi/latest/run.log
```
  Job ID: smart:658cb218-ccb8-4bb1-bd1b-fe0789382a5f
```
  - ... and 10 more failures.
- Test aes_ctr_fi has 1 failures.
  - 45.aes_ctr_fi.5413019645775047267172004540202358033280134857316535744366490878100881607049
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_ctr_fi/latest/run.log
```
  Job ID: smart:a6d5fff6-55f3-4193-873f-43797b02770c
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 16 failures:
- Test aes_control_fi has 16 failures.
  - 20.aes_control_fi.17424845125827474944740519474851561682668720555281364532229693876316645617599
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009176835 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009176835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 50.aes_control_fi.66925341205892366462934286903734890154585049173495203171853631780073708742551
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/50.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006983310 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006983310 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 4.aes_cipher_fi.18082237256183070022654129632764170397161927069765832242823133082565556849129
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008676478 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008676478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.aes_cipher_fi.10550208015618750431224210527989584874638641649336580922184849969314350234140
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016048941 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016048941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.107283921478062887275001032079086040015164464548645850089189669723976401631925
Line 1293, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3281960591 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3281960591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.102037889116837206743512601753659727443103453765725840305707772006478854779010
Line 1151, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1526306473 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1526306473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

3.aes_stress_all_with_rand_reset.88729312553953119233634288309658317432167715383180157551451513454178062684950
Line 1663, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1027619033 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1027619033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.18470079524143103421128075921507824086791031558506709213414390574247581997773
Line 1498, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 415067253 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 415067253 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.35878156963848405440284842362235499822493407479776642472800405968121849479140
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  22432017 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  22432017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.aes_stress_all_with_rand_reset.295538570564841303610567822308217510997402335865425744476193542774170853877
    Line 1015, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 581676313 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 581676313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 6.aes_core_fi.32489411306834579425775241803493558265870324969927462547408063165431349918006
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005378487 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005378487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_core_fi.57202844736080761200767780902299989099443627602051071444700564505618918762498
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008874350 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008874350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 4.aes_core_fi.89733024620187196733928016740701828927044428041383498523708401708242283177327
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051953872 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10051953872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```