AES/UNMASKED Simulation Results

Tuesday June 25 2024 23:02:40 UTC

GitHub Revision: `3fd3528c8c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44317642457786780768002458033256869318159334982704173107202396839344093642292

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	133.451us	1	1	100.00
V1	smoke	aes_smoke	15.000s	60.828us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	8.000s	61.974us	5	5	100.00
V1	csr_rw	aes_csr_rw	13.000s	82.270us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.032ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	7.000s	91.722us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	13.000s	114.803us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	13.000s	82.270us	20	20	100.00
		aes_csr_aliasing	7.000s	91.722us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	15.000s	60.828us	50	50	100.00
		aes_config_error	14.000s	60.288us	50	50	100.00
		aes_stress	10.000s	116.144us	50	50	100.00
V2	key_length	aes_smoke	15.000s	60.828us	50	50	100.00
		aes_config_error	14.000s	60.288us	50	50	100.00
		aes_stress	10.000s	116.144us	50	50	100.00
V2	back2back	aes_stress	10.000s	116.144us	50	50	100.00
		aes_b2b	18.000s	62.072us	50	50	100.00
V2	backpressure	aes_stress	10.000s	116.144us	50	50	100.00
V2	multi_message	aes_smoke	15.000s	60.828us	50	50	100.00
		aes_config_error	14.000s	60.288us	50	50	100.00
		aes_stress	10.000s	116.144us	50	50	100.00
		aes_alert_reset	14.000s	68.506us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	135.082us	50	50	100.00
		aes_config_error	14.000s	60.288us	50	50	100.00
		aes_alert_reset	14.000s	68.506us	50	50	100.00
V2	trigger_clear_test	aes_clear	20.000s	184.689us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	280.570us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	68.506us	50	50	100.00
V2	stress	aes_stress	10.000s	116.144us	50	50	100.00
V2	sideload	aes_stress	10.000s	116.144us	50	50	100.00
		aes_sideload	19.000s	135.500us	50	50	100.00
V2	deinitialization	aes_deinit	19.000s	93.203us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	4.857ms	10	10	100.00
V2	alert_test	aes_alert_test	18.000s	66.831us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	21.000s	556.010us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	21.000s	556.010us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	8.000s	61.974us	5	5	100.00
		aes_csr_rw	13.000s	82.270us	20	20	100.00
		aes_csr_aliasing	7.000s	91.722us	5	5	100.00
		aes_same_csr_outstanding	14.000s	214.665us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	8.000s	61.974us	5	5	100.00
		aes_csr_rw	13.000s	82.270us	20	20	100.00
		aes_csr_aliasing	7.000s	91.722us	5	5	100.00
		aes_same_csr_outstanding	14.000s	214.665us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	15.000s	348.861us	49	50	98.00
V2S	fault_inject	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_cipher_fi	51.000s	16.110ms	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	64.753us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	64.753us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	64.753us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	64.753us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	81.668us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	656.129us	5	5	100.00
		aes_tl_intg_err	20.000s	312.166us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	20.000s	312.166us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	68.506us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	64.753us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	15.000s	60.828us	50	50	100.00
		aes_stress	10.000s	116.144us	50	50	100.00
		aes_alert_reset	14.000s	68.506us	50	50	100.00
		aes_core_fi	52.000s	10.006ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	64.753us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	69.346us	50	50	100.00
		aes_stress	10.000s	116.144us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	116.144us	50	50	100.00
		aes_sideload	19.000s	135.500us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	69.346us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	69.346us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	69.346us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	69.346us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	69.346us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	116.144us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	116.144us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	121.427us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_cipher_fi	51.000s	16.110ms	319	350	91.14
		aes_ctr_fi	13.000s	89.737us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	121.427us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_cipher_fi	51.000s	16.110ms	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	16.110ms	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	121.427us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_ctr_fi	13.000s	89.737us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_cipher_fi	51.000s	16.110ms	319	350	91.14
		aes_ctr_fi	13.000s	89.737us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	68.506us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_cipher_fi	51.000s	16.110ms	319	350	91.14
		aes_ctr_fi	13.000s	89.737us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_cipher_fi	51.000s	16.110ms	319	350	91.14
		aes_ctr_fi	13.000s	89.737us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_ctr_fi	13.000s	89.737us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	121.427us	49	50	98.00
		aes_control_fi	48.000s	32.844ms	269	300	89.67
		aes_cipher_fi	51.000s	16.110ms	319	350	91.14
V2S		TOTAL			915	985	92.89
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.983m	23.938ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1522	1602	95.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.10	97.43	94.18	98.66	93.86	97.64	91.11	98.66	95.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 39 failures:
- Test aes_cipher_fi has 17 failures.
  - 23.aes_cipher_fi.80101883924375629329619708731842116642160720393856982392442567551242935894370
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:808bc338-e78d-4859-a324-c694800155a3
```
  - 34.aes_cipher_fi.63548898993100253036485648484057100481306315676812078585276561611543358201120
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_cipher_fi/latest/run.log
```
  Job ID: smart:f1546d71-530c-4c26-ac8f-66a836b5e9ad
```
  - ... and 15 more failures.
- Test aes_control_fi has 22 failures.
  - 36.aes_control_fi.35384842746931916144177775409284314981325495796431744593714646733217990922283
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_control_fi/latest/run.log
```
  Job ID: smart:fedc6ca2-cbf7-4f71-ba00-bae7fbfb37ea
```
  - 51.aes_control_fi.102315188877284434326561146094350302393434285531064603195788006528881640771773
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/51.aes_control_fi/latest/run.log
```
  Job ID: smart:131013f7-3b6d-4371-8d16-6cbbc647c722
```
  - ... and 20 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_cipher_fi has 14 failures.
  - 10.aes_cipher_fi.25104605724206089009804352868970583575584785723478596586352028490031894413949
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014749945 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014749945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_cipher_fi.55669180592479383430383009894281306146101565847646108850010877362749349720311
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009462820 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009462820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_control_fi has 9 failures.
  - 9.aes_control_fi.51560610979961373572780378208602954514120639104923483463778200460877589766923
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007837208 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007837208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 11.aes_control_fi.19273935109591843243762082393367035043506793783851395826687612487472955464123
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10035077848 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035077848 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.80877145280726169077959801188068386747122389911139863670437346139678579277480
Line 464, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4279050417 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4279050417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.66372110708779159021520599847544709755203986204743596834922341919241417523017
Line 1908, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1541182080 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1541182080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 8.aes_core_fi.97775584275287104866963164383129125849504159513161445281702944947918630717823
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10005635926 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005635926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_core_fi.1985872270893398012468296583036623449539760354175483650124248160091692393620
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10009755618 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009755618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.58415302972032137103842780233437928268058116757426210388683257444384653495502
Line 699, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 299053839 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 299053839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.56580186695290971123782406105881097570833494482468801008355985058911450875584
Line 726, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 736611515 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 736611515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_reseed has 1 failures.
  - 24.aes_reseed.3837132514933369545371994668321799201358224249995062260141789142711668945434
    Line 410, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_reseed/latest/run.log
```
  UVM_FATAL @  47689018 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @  47689018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 33.aes_fi.30966562819515963887815781731567298738052075197944906939859367542627122278430
    Line 1146, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 19653367 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 19633367 PS)
  UVM_ERROR @  19653367 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  19653367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 41.aes_core_fi.68263042927511431841491496174885549843981216348942485628349976249413036924756
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022454764 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022454764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```