AES/UNMASKED Simulation Results

Wednesday June 26 2024 23:02:36 UTC

GitHub Revision: `be1c4a4f52`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 44766564427213563291105655232733134394512207819884794315335669279596867428010

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	156.222us	1	1	100.00
V1	smoke	aes_smoke	4.000s	159.718us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	90.160us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	84.799us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	5.303ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	772.507us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	73.624us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	84.799us	20	20	100.00
		aes_csr_aliasing	5.000s	772.507us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	159.718us	50	50	100.00
		aes_config_error	10.000s	343.420us	50	50	100.00
		aes_stress	5.000s	122.485us	50	50	100.00
V2	key_length	aes_smoke	4.000s	159.718us	50	50	100.00
		aes_config_error	10.000s	343.420us	50	50	100.00
		aes_stress	5.000s	122.485us	50	50	100.00
V2	back2back	aes_stress	5.000s	122.485us	50	50	100.00
		aes_b2b	12.000s	449.942us	50	50	100.00
V2	backpressure	aes_stress	5.000s	122.485us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	159.718us	50	50	100.00
		aes_config_error	10.000s	343.420us	50	50	100.00
		aes_stress	5.000s	122.485us	50	50	100.00
		aes_alert_reset	7.000s	505.116us	49	50	98.00
V2	failure_test	aes_man_cfg_err	4.000s	54.930us	50	50	100.00
		aes_config_error	10.000s	343.420us	50	50	100.00
		aes_alert_reset	7.000s	505.116us	49	50	98.00
V2	trigger_clear_test	aes_clear	6.000s	675.332us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	2.346ms	1	1	100.00
V2	reset_recovery	aes_alert_reset	7.000s	505.116us	49	50	98.00
V2	stress	aes_stress	5.000s	122.485us	50	50	100.00
V2	sideload	aes_stress	5.000s	122.485us	50	50	100.00
		aes_sideload	5.000s	294.864us	50	50	100.00
V2	deinitialization	aes_deinit	4.000s	108.774us	50	50	100.00
V2	stress_all	aes_stress_all	29.000s	1.929ms	10	10	100.00
V2	alert_test	aes_alert_test	4.000s	240.575us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	5.000s	200.964us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	5.000s	200.964us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	90.160us	5	5	100.00
		aes_csr_rw	4.000s	84.799us	20	20	100.00
		aes_csr_aliasing	5.000s	772.507us	5	5	100.00
		aes_same_csr_outstanding	4.000s	123.656us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	90.160us	5	5	100.00
		aes_csr_rw	4.000s	84.799us	20	20	100.00
		aes_csr_aliasing	5.000s	772.507us	5	5	100.00
		aes_same_csr_outstanding	4.000s	123.656us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	8.000s	513.355us	50	50	100.00
V2S	fault_inject	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_cipher_fi	50.000s	31.536ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	66.024us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	66.024us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	66.024us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	66.024us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	106.299us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	1.685ms	5	5	100.00
		aes_tl_intg_err	5.000s	164.150us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	164.150us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	7.000s	505.116us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	66.024us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	159.718us	50	50	100.00
		aes_stress	5.000s	122.485us	50	50	100.00
		aes_alert_reset	7.000s	505.116us	49	50	98.00
		aes_core_fi	10.000s	10.089ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	66.024us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	129.872us	50	50	100.00
		aes_stress	5.000s	122.485us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	5.000s	122.485us	50	50	100.00
		aes_sideload	5.000s	294.864us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	129.872us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	129.872us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	129.872us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	129.872us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	129.872us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	5.000s	122.485us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	5.000s	122.485us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	46.350m	200.000ms	46	50	92.00
V2S	sec_cm_main_fsm_redun	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_cipher_fi	50.000s	31.536ms	323	350	92.29
		aes_ctr_fi	4.000s	241.153us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	46.350m	200.000ms	46	50	92.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_cipher_fi	50.000s	31.536ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	31.536ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	46.350m	200.000ms	46	50	92.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_ctr_fi	4.000s	241.153us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_cipher_fi	50.000s	31.536ms	323	350	92.29
		aes_ctr_fi	4.000s	241.153us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	7.000s	505.116us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_cipher_fi	50.000s	31.536ms	323	350	92.29
		aes_ctr_fi	4.000s	241.153us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_cipher_fi	50.000s	31.536ms	323	350	92.29
		aes_ctr_fi	4.000s	241.153us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_ctr_fi	4.000s	241.153us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	46.350m	200.000ms	46	50	92.00
		aes_control_fi	52.000s	75.003ms	275	300	91.67
		aes_cipher_fi	50.000s	31.536ms	323	350	92.29
V2S		TOTAL			928	985	94.21
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	42.000s	1.665ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.44	94.22	98.75	93.80	97.64	91.11	98.85	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 14 failures.
  - 6.aes_control_fi.69873077104190246424875319787984266104987527265284976639056109131032137180081
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  Job ID: smart:2f859b62-a545-49f9-ba23-f24fdb2e1f79
```
  - 14.aes_control_fi.98386179514070132240197238602885687971333956337690760093695965566605375015707
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job ID: smart:ccf257dd-b91d-4619-bc33-096b1d238cfc
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 16 failures.
  - 8.aes_cipher_fi.98889633519911171374477298994795110293057871884349429593096975203725864397295
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  Job ID: smart:71a0c041-0542-4af8-a5e9-7698860f929a
```
  - 17.aes_cipher_fi.31966171681058458342080664869645879986694976425373134625128749897752623699306
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_cipher_fi/latest/run.log
```
  Job ID: smart:cdf774cb-805d-472b-9df5-1a105ddcc856
```
  - ... and 14 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 15.aes_control_fi.30172305148263244808406030860888250994181619522258661369384151878527423232692
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006610481 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006610481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 85.aes_control_fi.3908087177666753295904498990627277844242908554744295588527573370228051852028
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/85.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011716565 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011716565 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 57.aes_cipher_fi.90432157379776929237177706287820991529783627293369634390062462564274212644291
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/57.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10025535994 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10025535994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 85.aes_cipher_fi.104895264349642644445553579840398088189059959091968994991731322414960243471409
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/85.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003497353 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003497353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.106936354730125384827101605917672701299110390626097415280380544179307198508240
Line 950, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 410778450 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 410778450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.62202328579908054982071221271901293102101735606857472036030148159371750033546
Line 1877, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1149338125 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1149338125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.4234437761688540419708201621194646138700534848444449665558943356227980521449
Line 785, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 209387958 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 209387958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.36609356738894808035495512390261523958905226960377268323890123404669177241003
Line 1446, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1665129783 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1665129783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

4.aes_fi.99424047401757447981625489221952100868475172656376682963414624400646578636685
Line 14070, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_fi/latest/run.log

  UVM_FATAL @  57663836 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  57663836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_fi.81645200610169757006783835458714775505917308796883574205272570799067799572693
Line 10549, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_fi/latest/run.log

  UVM_FATAL @ 108874190 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 108874190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test aes_fi has 1 failures.
  - 48.aes_fi.26194018791413695226895900074561313463548274204217801470497166773128769426823
    Line 23998754, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_cipher_fi has 1 failures.
  - 175.aes_cipher_fi.77315638349465460001061441875996375058278615488248224015994748578949697776030
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/175.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd aes_reg_block.status (addr=*) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.1048122822352682775954292691559136762421574063211484888693596559187214348280
    Line 331, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2022659091 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd aes_reg_block.status (addr=0xdcade184)
  UVM_INFO @ 2022659091 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 21.aes_core_fi.86291605401279618976842968063672886727432267709262652986128804597126429220698
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10088799010 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10088799010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 25.aes_alert_reset.21192501147884735738489831671318769080630851661907827953368425885962407763873
    Line 1638, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 4662403 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 4652302 PS)
  UVM_ERROR @   4662403 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   4662403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 44.aes_fi.62589497908029779916311016107117782535442147048842004612605423659954881468296
    Line 4015, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 21874679 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 21853846 PS)
  UVM_ERROR @  21874679 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  21874679 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_control_fi has 1 failures.
  - 89.aes_control_fi.12156309922428814215616802282859842745614084466573578334389194464926359510367
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/89.aes_control_fi/latest/run.log
```
  UVM_ERROR @  40002546 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_tl_agent_aes_reg_block.sequencer' for sequence 'm_tl_host_base_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  40002546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```