AES/UNMASKED Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: `8db2a18db1`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	76.962us	1	1	100.00
V1	smoke	aes_smoke	14.000s	127.341us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	95.043us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	117.136us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	633.099us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	486.133us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	152.312us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	117.136us	20	20	100.00
		aes_csr_aliasing	5.000s	486.133us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	14.000s	127.341us	50	50	100.00
		aes_config_error	14.000s	86.163us	50	50	100.00
		aes_stress	14.000s	151.218us	50	50	100.00
V2	key_length	aes_smoke	14.000s	127.341us	50	50	100.00
		aes_config_error	14.000s	86.163us	50	50	100.00
		aes_stress	14.000s	151.218us	50	50	100.00
V2	back2back	aes_stress	14.000s	151.218us	50	50	100.00
		aes_b2b	21.000s	261.455us	50	50	100.00
V2	backpressure	aes_stress	14.000s	151.218us	50	50	100.00
V2	multi_message	aes_smoke	14.000s	127.341us	50	50	100.00
		aes_config_error	14.000s	86.163us	50	50	100.00
		aes_stress	14.000s	151.218us	50	50	100.00
		aes_alert_reset	9.000s	266.325us	49	50	98.00
V2	failure_test	aes_man_cfg_err	8.000s	75.886us	50	50	100.00
		aes_config_error	14.000s	86.163us	50	50	100.00
		aes_alert_reset	9.000s	266.325us	49	50	98.00
V2	trigger_clear_test	aes_clear	11.000s	184.808us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	297.057us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	266.325us	49	50	98.00
V2	stress	aes_stress	14.000s	151.218us	50	50	100.00
V2	sideload	aes_stress	14.000s	151.218us	50	50	100.00
		aes_sideload	14.000s	107.637us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	215.276us	50	50	100.00
V2	stress_all	aes_stress_all	24.000s	744.994us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	62.469us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	251.532us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	251.532us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	95.043us	5	5	100.00
		aes_csr_rw	4.000s	117.136us	20	20	100.00
		aes_csr_aliasing	5.000s	486.133us	5	5	100.00
		aes_same_csr_outstanding	5.817m	10.018ms	19	20	95.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	95.043us	5	5	100.00
		aes_csr_rw	4.000s	117.136us	20	20	100.00
		aes_csr_aliasing	5.000s	486.133us	5	5	100.00
		aes_same_csr_outstanding	5.817m	10.018ms	19	20	95.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	13.000s	74.386us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_cipher_fi	47.000s	16.445ms	314	350	89.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	89.542us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	89.542us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	89.542us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	89.542us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	97.920us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.606ms	5	5	100.00
		aes_tl_intg_err	6.000s	2.274ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	2.274ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	266.325us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	89.542us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	14.000s	127.341us	50	50	100.00
		aes_stress	14.000s	151.218us	50	50	100.00
		aes_alert_reset	9.000s	266.325us	49	50	98.00
		aes_core_fi	44.000s	10.003ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	89.542us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	9.000s	85.799us	50	50	100.00
		aes_stress	14.000s	151.218us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	151.218us	50	50	100.00
		aes_sideload	14.000s	107.637us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	9.000s	85.799us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	9.000s	85.799us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	9.000s	85.799us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	9.000s	85.799us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	9.000s	85.799us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	151.218us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	151.218us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	141.926us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_cipher_fi	47.000s	16.445ms	314	350	89.71
		aes_ctr_fi	13.000s	70.322us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	141.926us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_cipher_fi	47.000s	16.445ms	314	350	89.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	16.445ms	314	350	89.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	141.926us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_ctr_fi	13.000s	70.322us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_cipher_fi	47.000s	16.445ms	314	350	89.71
		aes_ctr_fi	13.000s	70.322us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	266.325us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_cipher_fi	47.000s	16.445ms	314	350	89.71
		aes_ctr_fi	13.000s	70.322us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_cipher_fi	47.000s	16.445ms	314	350	89.71
		aes_ctr_fi	13.000s	70.322us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_ctr_fi	13.000s	70.322us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	141.926us	50	50	100.00
		aes_control_fi	46.000s	82.913ms	274	300	91.33
		aes_cipher_fi	47.000s	16.445ms	314	350	89.71
V2S		TOTAL			917	985	93.10
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	8.500m	35.954ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1522	1602	95.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	11	84.62
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.50	94.35	98.79	93.51	97.64	91.11	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 39 failures:
- Test aes_control_fi has 12 failures.
  - 8.aes_control_fi.1127254944216899563102515176957313504032984245968706389480227618214333295076
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  Job ID: smart:31d632cf-f569-4de7-b363-7574974c38d2
```
  - 15.aes_control_fi.4854673935992611670971722901829994997946197791220333465912952066171874406588
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:eff69521-b5c6-44cd-9fb1-8a10011d292c
```
  - ... and 10 more failures.
- Test aes_ctr_fi has 1 failures.
  - 20.aes_ctr_fi.23117218000688224469521688542112140025073232499465367777549923718992150189960
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_ctr_fi/latest/run.log
```
  Job ID: smart:23591170-3e9f-4d9e-bded-e91332301f07
```
- Test aes_cipher_fi has 26 failures.
  - 23.aes_cipher_fi.25131220912228706996892349547868217647194759128459197373088209930172858401092
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bfcea13d-11b8-4104-8ad9-b15d1b1567b5
```
  - 31.aes_cipher_fi.77696223605886832094012001926241270057868161462585356476986209960289585335538
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  Job ID: smart:15bf91c5-e072-4b44-b221-3811740efb71
```
  - ... and 24 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_control_fi has 14 failures.
  - 1.aes_control_fi.43736875988284416786366409425614711228880934862294537761853452514670240205352
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005763501 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005763501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_control_fi.18649758668859821615305734320550021101022193590425072803517097692155688178425
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006728087 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006728087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 48.aes_cipher_fi.25668616083337435940070896626688285774708414095461350561882248716648969907837
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/48.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012603062 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012603062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_cipher_fi.100962376202911243727394634729514763871350515672004676269452553520064626785098
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009534200 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009534200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

1.aes_stress_all_with_rand_reset.81154278288681568750779574213421465953480888324609990368567236498124524193092
Line 1389, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15500948998 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 15500948998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.73162301152101247004970788601825520296705727572591358757454894109435719440985
Line 739, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 35954226260 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 35954226260 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.13614815101472224108260374994530258890659567108017055684662470796639226290138
Line 779, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 749136326 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 749136326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.64539644358511878805319205563419971027126898641581987849657805116238970302710
Line 877, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 400485909 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 400485909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 6.aes_core_fi.65217025560970075087905072661048453814245548637861219854459536719452869304488
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011451692 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011451692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.aes_core_fi.22943478906157682858548620055719706057687616379546983059371660559900783838125
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003004825 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003004825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 17.aes_core_fi.74482923277654588007844291941186252079724654104964193611321928232381333004406
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10081624377 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10081624377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_core_fi.70359673978702535826448494584175508071435129746740487453718404011357912013248
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021840731 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021840731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 7.aes_stress_all_with_rand_reset.67268103552373656542149526820337365613258831406956169459550320598286133071635
    Line 598, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 526767388 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 526767388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_same_csr_outstanding has 1 failures.
  - 10.aes_same_csr_outstanding.86849479563411412690762046860766664774312065786864857725064953459827516911702
    Line 295, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10018039184 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x685ceb84) == 0x0
  UVM_INFO @ 10018039184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 45.aes_alert_reset.78229507951040165107109601066523406019828146751987735031018125554271509098498
    Line 2122, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/45.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 7825950 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 7815641 PS)
  UVM_ERROR @   7825950 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   7825950 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```