AES/UNMASKED Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: `3d5220a43f`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	81.886us	1	1	100.00
V1	smoke	aes_smoke	13.000s	60.719us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	89.894us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	66.547us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	1.014ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	988.173us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	66.033us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	66.547us	20	20	100.00
		aes_csr_aliasing	5.000s	988.173us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	60.719us	50	50	100.00
		aes_config_error	15.000s	548.124us	50	50	100.00
		aes_stress	7.000s	301.043us	50	50	100.00
V2	key_length	aes_smoke	13.000s	60.719us	50	50	100.00
		aes_config_error	15.000s	548.124us	50	50	100.00
		aes_stress	7.000s	301.043us	50	50	100.00
V2	back2back	aes_stress	7.000s	301.043us	50	50	100.00
		aes_b2b	13.000s	169.680us	50	50	100.00
V2	backpressure	aes_stress	7.000s	301.043us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	60.719us	50	50	100.00
		aes_config_error	15.000s	548.124us	50	50	100.00
		aes_stress	7.000s	301.043us	50	50	100.00
		aes_alert_reset	9.000s	104.132us	50	50	100.00
V2	failure_test	aes_man_cfg_err	5.000s	51.565us	50	50	100.00
		aes_config_error	15.000s	548.124us	50	50	100.00
		aes_alert_reset	9.000s	104.132us	50	50	100.00
V2	trigger_clear_test	aes_clear	9.000s	535.310us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	288.685us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	104.132us	50	50	100.00
V2	stress	aes_stress	7.000s	301.043us	50	50	100.00
V2	sideload	aes_stress	7.000s	301.043us	50	50	100.00
		aes_sideload	13.000s	554.826us	50	50	100.00
V2	deinitialization	aes_deinit	15.000s	233.711us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	1.878ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	54.344us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	658.914us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	658.914us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	89.894us	5	5	100.00
		aes_csr_rw	4.000s	66.547us	20	20	100.00
		aes_csr_aliasing	5.000s	988.173us	5	5	100.00
		aes_same_csr_outstanding	5.000s	168.309us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	89.894us	5	5	100.00
		aes_csr_rw	4.000s	66.547us	20	20	100.00
		aes_csr_aliasing	5.000s	988.173us	5	5	100.00
		aes_same_csr_outstanding	5.000s	168.309us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	8.000s	183.408us	50	50	100.00
V2S	fault_inject	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_cipher_fi	50.000s	32.169ms	314	350	89.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	13.000s	285.934us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	13.000s	285.934us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	13.000s	285.934us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	13.000s	285.934us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	295.387us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	376.191us	5	5	100.00
		aes_tl_intg_err	6.000s	657.430us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	657.430us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	104.132us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	13.000s	285.934us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	60.719us	50	50	100.00
		aes_stress	7.000s	301.043us	50	50	100.00
		aes_alert_reset	9.000s	104.132us	50	50	100.00
		aes_core_fi	1.617m	10.041ms	69	70	98.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	13.000s	285.934us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	69.334us	50	50	100.00
		aes_stress	7.000s	301.043us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	7.000s	301.043us	50	50	100.00
		aes_sideload	13.000s	554.826us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	69.334us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	69.334us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	69.334us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	69.334us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	69.334us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	7.000s	301.043us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	7.000s	301.043us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	14.000s	81.794us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_cipher_fi	50.000s	32.169ms	314	350	89.71
		aes_ctr_fi	8.000s	52.469us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	14.000s	81.794us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_cipher_fi	50.000s	32.169ms	314	350	89.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	50.000s	32.169ms	314	350	89.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	14.000s	81.794us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_ctr_fi	8.000s	52.469us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_cipher_fi	50.000s	32.169ms	314	350	89.71
		aes_ctr_fi	8.000s	52.469us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	104.132us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_cipher_fi	50.000s	32.169ms	314	350	89.71
		aes_ctr_fi	8.000s	52.469us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_cipher_fi	50.000s	32.169ms	314	350	89.71
		aes_ctr_fi	8.000s	52.469us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_ctr_fi	8.000s	52.469us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	14.000s	81.794us	50	50	100.00
		aes_control_fi	43.000s	24.653ms	282	300	94.00
		aes_cipher_fi	50.000s	32.169ms	314	350	89.71
V2S		TOTAL			930	985	94.42
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	4.367m	39.508ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1537	1602	95.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.55	94.48	98.75	93.77	97.72	91.11	98.85	96.41

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_cipher_fi has 18 failures.
  - 0.aes_cipher_fi.6948547512349587006622395667665757907252547457072893423803542774556071556520
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b83eed08-192b-4efd-a35d-09a094a09003
```
  - 1.aes_cipher_fi.58572422210782675189188718777612687081272608824624363276995803053617725234849
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2ea8e2ef-8b9c-477f-acab-6efa32bf4d9b
```
  - ... and 16 more failures.
- Test aes_control_fi has 11 failures.
  - 17.aes_control_fi.62835978557285082191921799300597353070209687211187178880013757630723411191992
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job ID: smart:9f2e077c-a1d7-48e0-8034-b4c1bbec6b05
```
  - 46.aes_control_fi.48054315841107440788197696042478502087772408347097392555709584111022693400277
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/46.aes_control_fi/latest/run.log
```
  Job ID: smart:c62206b1-8196-4a34-b8f4-0c91c6aee2ae
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_cipher_fi has 18 failures.
  - 10.aes_cipher_fi.94318932803310453209829969636633226720620876746381438313758676357832316837219
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010101847 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010101847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_cipher_fi.20291820327655407449887417669702001148938463091588034574190713115271469496627
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002880564 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002880564 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 15.aes_control_fi.87560230565074932639227298447005602699430835895653106148811282044638732192655
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004331929 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004331929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 21.aes_control_fi.107843309633733353990569919513977070340143368226321584100737320527838963627214
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007270791 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007270791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.33279562650202596756654466241192287022438709881314386061871178643750214935227
Line 532, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6066117174 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6066117174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.82724488038387853966389317856479883505869654309071664901473160771121047669076
Line 992, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 548273704 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 548273704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

3.aes_stress_all_with_rand_reset.61457735742768355062136517693137626790212013440112136383124212122408745264114
Line 1832, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 683045448 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 683045448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.aes_stress_all_with_rand_reset.32476436403242539964274046323256748761320315309062356855751062356259480073968
Line 630, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 480176972 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 480176972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (cip_base_vseq.sv:555) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.43243785792214919930877689454077681379414521511663006784151080966895710899488
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  59937169 ps: (cip_base_vseq.sv:555) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  59937169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 32.aes_core_fi.80964633290409908880429250461382808023891333407111816324799676970564726375858
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10040927333 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x128fd784) == 0x0
  UVM_INFO @ 10040927333 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```