AES/UNMASKED Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: `b33f0bcb4a`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	67.177us	1	1	100.00
V1	smoke	aes_smoke	8.000s	150.158us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	59.956us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.200m	10.022ms	19	20	95.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	816.636us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	99.719us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	64.858us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.200m	10.022ms	19	20	95.00
		aes_csr_aliasing	4.000s	99.719us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	8.000s	150.158us	50	50	100.00
		aes_config_error	8.000s	72.569us	50	50	100.00
		aes_stress	9.000s	132.383us	50	50	100.00
V2	key_length	aes_smoke	8.000s	150.158us	50	50	100.00
		aes_config_error	8.000s	72.569us	50	50	100.00
		aes_stress	9.000s	132.383us	50	50	100.00
V2	back2back	aes_stress	9.000s	132.383us	50	50	100.00
		aes_b2b	11.000s	1.844ms	50	50	100.00
V2	backpressure	aes_stress	9.000s	132.383us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	150.158us	50	50	100.00
		aes_config_error	8.000s	72.569us	50	50	100.00
		aes_stress	9.000s	132.383us	50	50	100.00
		aes_alert_reset	10.000s	166.249us	50	50	100.00
V2	failure_test	aes_man_cfg_err	12.000s	101.924us	50	50	100.00
		aes_config_error	8.000s	72.569us	50	50	100.00
		aes_alert_reset	10.000s	166.249us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	666.131us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	282.986us	1	1	100.00
V2	reset_recovery	aes_alert_reset	10.000s	166.249us	50	50	100.00
V2	stress	aes_stress	9.000s	132.383us	50	50	100.00
V2	sideload	aes_stress	9.000s	132.383us	50	50	100.00
		aes_sideload	8.000s	249.386us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	206.397us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	623.596us	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	95.455us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	70.664us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	70.664us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	59.956us	5	5	100.00
		aes_csr_rw	1.200m	10.022ms	19	20	95.00
		aes_csr_aliasing	4.000s	99.719us	5	5	100.00
		aes_same_csr_outstanding	5.000s	97.980us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	59.956us	5	5	100.00
		aes_csr_rw	1.200m	10.022ms	19	20	95.00
		aes_csr_aliasing	4.000s	99.719us	5	5	100.00
		aes_same_csr_outstanding	5.000s	97.980us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	13.000s	92.959us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	67.639us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	67.639us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	67.639us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	67.639us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	82.976us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	18.000s	6.038ms	5	5	100.00
		aes_tl_intg_err	7.000s	3.823ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	3.823ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	10.000s	166.249us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	67.639us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	150.158us	50	50	100.00
		aes_stress	9.000s	132.383us	50	50	100.00
		aes_alert_reset	10.000s	166.249us	50	50	100.00
		aes_core_fi	4.100m	10.016ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	67.639us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	58.939us	50	50	100.00
		aes_stress	9.000s	132.383us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	132.383us	50	50	100.00
		aes_sideload	8.000s	249.386us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	58.939us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	58.939us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	58.939us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	58.939us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	58.939us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	132.383us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	132.383us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	70.634us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	323	350	92.29
		aes_ctr_fi	9.000s	57.203us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	70.634us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	10.003ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	70.634us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_ctr_fi	9.000s	57.203us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	323	350	92.29
		aes_ctr_fi	9.000s	57.203us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	10.000s	166.249us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	323	350	92.29
		aes_ctr_fi	9.000s	57.203us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	323	350	92.29
		aes_ctr_fi	9.000s	57.203us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_ctr_fi	9.000s	57.203us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	70.634us	50	50	100.00
		aes_control_fi	49.000s	32.836ms	275	300	91.67
		aes_cipher_fi	48.000s	10.003ms	323	350	92.29
V2S		TOTAL			929	985	94.31
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.133m	15.374ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.46	94.26	98.77	93.51	97.72	91.11	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 31 failures:
- Test aes_cipher_fi has 19 failures.
  - 7.aes_cipher_fi.31631677740936645376057592844678318092265652225385167578643984790367784575942
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_cipher_fi/latest/run.log
```
  Job ID: smart:bd2cef51-857e-428d-9d57-d51ba853b4b2
```
  - 14.aes_cipher_fi.11593300811453383967336245026815159713337735318512900540019779069558143769089
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job ID: smart:15483ee1-1ad3-4794-a0d1-83e9e1370dfd
```
  - ... and 17 more failures.
- Test aes_control_fi has 11 failures.
  - 16.aes_control_fi.22190119001737298739980248154383100667594609392054527426391309728869410392986
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  Job ID: smart:3eaf96f3-419e-4795-8a11-708a974c5a8e
```
  - 63.aes_control_fi.37266811633038604091691445515797488153050688230819586098998517622153452961900
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  Job ID: smart:96465c87-aaf2-456e-b3f2-861dfe6cc87a
```
  - ... and 9 more failures.
- Test aes_ctr_fi has 1 failures.
  - 21.aes_ctr_fi.20117669198406316303872211886301425352468319906504655362797109413749930354341
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_ctr_fi/latest/run.log
```
  Job ID: smart:13d5263b-30fc-4b73-90bf-a49eb1862f77
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 14 failures:
- Test aes_control_fi has 14 failures.
  - 6.aes_control_fi.107260208317113609051547168281514738618810410252762041140799327905766513492262
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008957959 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008957959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_control_fi.66849705964992706013819752201032310403143793201292062157388838699609814312067
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003506452 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003506452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 25.aes_cipher_fi.102913056576094645187922824783485539104260972045354741418706823438729014847372
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009028734 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009028734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 60.aes_cipher_fi.31918864496967982834997199182194233728037490675463403491462119349409153364689
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005146387 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005146387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.24252363460960546803997879222777309511098997260230207237070725858227647991816
Line 655, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1271063776 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1271063776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.51216204182942887136677549697109767147055331208347635214346236763872119517051
Line 469, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15374072505 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 15374072505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.7483516383818045223514445140023455059359330915293809585823850542882224407816
Line 798, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 179120819 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 179120819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.49903511002714422158471107653544867403719207208141486029938066461369346024618
Line 537, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 193607807 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 193607807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 23.aes_core_fi.52229022629982381772363249720355995280541640045373082744292578115581118568919
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004253030 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004253030 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 27.aes_core_fi.7693944842597943088043747296745559549850373537788947843343349064587248964263
    Line 330, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/27.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004982318 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004982318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.64773896093860515576530930665079039632114723570420720760213294857269805243839
    Line 593, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 103715365 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 103705365 PS)
  UVM_ERROR @ 103715365 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 103715365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_reseed_vseq.sv:28) [aes_reseed_vseq] Check failed request_seen == *'b* (* [*] vs * [*]) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 8.aes_stress_all.90399671026295421937939624838623442118453817029894988912780298358858046597399
    Line 37691, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all/latest/run.log
```
  UVM_FATAL @ 2453609303 ps: (aes_reseed_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed request_seen == 1'b1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 2453609303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*) == * has 1 failures:
- Test aes_csr_rw has 1 failures.
  - 14.aes_csr_rw.36046944830002040989299518210508714539561374939279056930549426992298382187567
    Line 286, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_csr_rw/latest/run.log
```
  UVM_FATAL @ 10022040965 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x8839f384) == 0x0
  UVM_INFO @ 10022040965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 26.aes_core_fi.103336707042348835154517019263755630626243530272193146375193108494266941085252
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/26.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016456591 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x101cf984) == 0x0
  UVM_INFO @ 10016456591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```