AES/UNMASKED Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	54.175us	1	1	100.00
V1	smoke	aes_smoke	11.000s	534.834us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	84.782us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	78.126us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	337.404us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	207.596us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	153.617us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	78.126us	20	20	100.00
		aes_csr_aliasing	6.000s	207.596us	5	5	100.00
V1		TOTAL			105	106	99.06
V2	algorithm	aes_smoke	11.000s	534.834us	50	50	100.00
		aes_config_error	14.000s	208.625us	50	50	100.00
		aes_stress	9.000s	210.918us	50	50	100.00
V2	key_length	aes_smoke	11.000s	534.834us	50	50	100.00
		aes_config_error	14.000s	208.625us	50	50	100.00
		aes_stress	9.000s	210.918us	50	50	100.00
V2	back2back	aes_stress	9.000s	210.918us	50	50	100.00
		aes_b2b	16.000s	133.888us	50	50	100.00
V2	backpressure	aes_stress	9.000s	210.918us	50	50	100.00
V2	multi_message	aes_smoke	11.000s	534.834us	50	50	100.00
		aes_config_error	14.000s	208.625us	50	50	100.00
		aes_stress	9.000s	210.918us	50	50	100.00
		aes_alert_reset	14.000s	299.533us	50	50	100.00
V2	failure_test	aes_man_cfg_err	13.000s	108.646us	50	50	100.00
		aes_config_error	14.000s	208.625us	50	50	100.00
		aes_alert_reset	14.000s	299.533us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	86.119us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	309.152us	1	1	100.00
V2	reset_recovery	aes_alert_reset	14.000s	299.533us	50	50	100.00
V2	stress	aes_stress	9.000s	210.918us	50	50	100.00
V2	sideload	aes_stress	9.000s	210.918us	50	50	100.00
		aes_sideload	9.000s	126.656us	50	50	100.00
V2	deinitialization	aes_deinit	13.000s	96.867us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	2.847ms	10	10	100.00
V2	alert_test	aes_alert_test	17.000s	60.108us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	81.600us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	81.600us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	84.782us	5	5	100.00
		aes_csr_rw	3.000s	78.126us	20	20	100.00
		aes_csr_aliasing	6.000s	207.596us	5	5	100.00
		aes_same_csr_outstanding	5.000s	65.128us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	84.782us	5	5	100.00
		aes_csr_rw	3.000s	78.126us	20	20	100.00
		aes_csr_aliasing	6.000s	207.596us	5	5	100.00
		aes_same_csr_outstanding	5.000s	65.128us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	67.834us	50	50	100.00
V2S	fault_inject	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_cipher_fi	49.000s	30.323ms	331	350	94.57
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	146.422us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	146.422us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	146.422us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	146.422us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	173.685us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	865.662us	5	5	100.00
		aes_tl_intg_err	5.000s	1.358ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	1.358ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	14.000s	299.533us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	146.422us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	11.000s	534.834us	50	50	100.00
		aes_stress	9.000s	210.918us	50	50	100.00
		aes_alert_reset	14.000s	299.533us	50	50	100.00
		aes_core_fi	48.000s	10.002ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	146.422us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	102.241us	50	50	100.00
		aes_stress	9.000s	210.918us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	210.918us	50	50	100.00
		aes_sideload	9.000s	126.656us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	102.241us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	102.241us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	102.241us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	102.241us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	102.241us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	210.918us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	210.918us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	27.483m	200.000ms	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_cipher_fi	49.000s	30.323ms	331	350	94.57
		aes_ctr_fi	13.000s	82.309us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	27.483m	200.000ms	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_cipher_fi	49.000s	30.323ms	331	350	94.57
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	30.323ms	331	350	94.57
V2S	sec_cm_ctr_fsm_sparse	aes_fi	27.483m	200.000ms	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_ctr_fi	13.000s	82.309us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_cipher_fi	49.000s	30.323ms	331	350	94.57
		aes_ctr_fi	13.000s	82.309us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	14.000s	299.533us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_cipher_fi	49.000s	30.323ms	331	350	94.57
		aes_ctr_fi	13.000s	82.309us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_cipher_fi	49.000s	30.323ms	331	350	94.57
		aes_ctr_fi	13.000s	82.309us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_ctr_fi	13.000s	82.309us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	27.483m	200.000ms	49	50	98.00
		aes_control_fi	45.000s	10.005ms	274	300	91.33
		aes_cipher_fi	49.000s	30.323ms	331	350	94.57
V2S		TOTAL			933	985	94.72
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.450m	17.093ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1539	1602	96.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	6	85.71
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.08	97.41	94.14	98.73	93.51	97.64	91.11	98.66	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 21 failures:
- Test aes_cipher_fi has 10 failures.
  - 12.aes_cipher_fi.72421933140430232510271439844089260908364745566487293929372841477371322502635
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1bee776a-502a-42ba-887e-1899e661dc9f
```
  - 40.aes_cipher_fi.52022620924024711328239574047707065910864768828267206109782644554179501757570
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job ID: smart:1e3eb32b-20b9-43bd-b123-7bbde684cab9
```
  - ... and 8 more failures.
- Test aes_control_fi has 11 failures.
  - 56.aes_control_fi.18296985363144486929405023543225991661565268563421662453690787184485914566844
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_control_fi/latest/run.log
```
  Job ID: smart:a72b86c3-0984-42dc-a13e-b26f0092ef1d
```
  - 58.aes_control_fi.35180223527061201837700599584446106924202045870976016191354368165326782488105
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/58.aes_control_fi/latest/run.log
```
  Job ID: smart:d382f39a-c49b-491f-9133-c80c77ccd0e9
```
  - ... and 9 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_control_fi has 15 failures.
  - 0.aes_control_fi.52548675135161047561236051460721127085630018825338923819968941383890921909968
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009019134 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009019134 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.aes_control_fi.29385008775036509418994009438373360662373585436838176973158762480327765601896
    Line 333, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011389692 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011389692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 4.aes_cipher_fi.64954208663015709414718825743364693366645883022668354474210266523684517369157
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10029761894 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10029761894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_cipher_fi.108191205709692114124231038470035092778687768899734163587378739800862966671207
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003766745 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003766745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

1.aes_stress_all_with_rand_reset.50962237120372865441542380874527690291771954394493402170319104965178670336211
Line 1008, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 732291986 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 732291986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.96937435745393890457048088639563642148157547343461719028863090528951252717021
Line 791, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 417991977 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 417991977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 30.aes_core_fi.83702777931595229232381540149095982654272201048423363455386231201872817045957
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10141214331 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10141214331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 54.aes_core_fi.72586336893232113079236078513195913165075832357290773843854529467311141940992
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/54.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10001873573 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10001873573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

0.aes_stress_all_with_rand_reset.94438403932568004358674102149372218881481872922928523851510310061598643272117
Line 1242, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 328893961 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 328893961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.55683641117814833601782380480121004205586889918157802616714812600681204023717
Line 1681, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3732783031 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 3732783031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:840) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 6.aes_csr_mem_rw_with_rand_reset.56648513816680375406643095535380280654072014268651152340867416149958499007690
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 237442713 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 237442713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_fi has 1 failures.
  - 17.aes_fi.85707163433735848361363507785829754939379103116854106079983326118224058253164
    Line 11483469, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/17.aes_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 59.aes_core_fi.13546042305916809211428235728971215543532664555874181629267990930803886863372
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10101659546 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x74058384) == 0x0
  UVM_INFO @ 10101659546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```