AES/UNMASKED Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	9.000s	78.328us	1	1	100.00
V1	smoke	aes_smoke	5.000s	92.047us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	9.000s	58.283us	5	5	100.00
V1	csr_rw	aes_csr_rw	8.000s	64.128us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.412ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.633m	10.081ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	8.000s	140.678us	19	20	95.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	8.000s	64.128us	20	20	100.00
		aes_csr_aliasing	1.633m	10.081ms	4	5	80.00
V1		TOTAL			104	106	98.11
V2	algorithm	aes_smoke	5.000s	92.047us	50	50	100.00
		aes_config_error	12.000s	350.356us	50	50	100.00
		aes_stress	9.000s	68.577us	50	50	100.00
V2	key_length	aes_smoke	5.000s	92.047us	50	50	100.00
		aes_config_error	12.000s	350.356us	50	50	100.00
		aes_stress	9.000s	68.577us	50	50	100.00
V2	back2back	aes_stress	9.000s	68.577us	50	50	100.00
		aes_b2b	10.000s	127.884us	50	50	100.00
V2	backpressure	aes_stress	9.000s	68.577us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	92.047us	50	50	100.00
		aes_config_error	12.000s	350.356us	50	50	100.00
		aes_stress	9.000s	68.577us	50	50	100.00
		aes_alert_reset	6.000s	181.223us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	61.974us	50	50	100.00
		aes_config_error	12.000s	350.356us	50	50	100.00
		aes_alert_reset	6.000s	181.223us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	78.958us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	492.653us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	181.223us	50	50	100.00
V2	stress	aes_stress	9.000s	68.577us	50	50	100.00
V2	sideload	aes_stress	9.000s	68.577us	50	50	100.00
		aes_sideload	6.000s	63.910us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	351.330us	50	50	100.00
V2	stress_all	aes_stress_all	37.000s	2.779ms	9	10	90.00
V2	alert_test	aes_alert_test	8.000s	57.320us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	78.374us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	78.374us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	9.000s	58.283us	5	5	100.00
		aes_csr_rw	8.000s	64.128us	20	20	100.00
		aes_csr_aliasing	1.633m	10.081ms	4	5	80.00
		aes_same_csr_outstanding	1.883m	10.056ms	18	20	90.00
V2	tl_d_partial_access	aes_csr_hw_reset	9.000s	58.283us	5	5	100.00
		aes_csr_rw	8.000s	64.128us	20	20	100.00
		aes_csr_aliasing	1.633m	10.081ms	4	5	80.00
		aes_same_csr_outstanding	1.883m	10.056ms	18	20	90.00
V2		TOTAL			498	501	99.40
V2S	reseeding	aes_reseed	15.000s	142.987us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_cipher_fi	48.000s	20.761ms	308	350	88.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	370.107us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	370.107us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	370.107us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	370.107us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	9.000s	1.097ms	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	1.730ms	5	5	100.00
		aes_tl_intg_err	9.000s	228.610us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	228.610us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	181.223us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	370.107us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	92.047us	50	50	100.00
		aes_stress	9.000s	68.577us	50	50	100.00
		aes_alert_reset	6.000s	181.223us	50	50	100.00
		aes_core_fi	6.033m	10.017ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	370.107us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	119.904us	50	50	100.00
		aes_stress	9.000s	68.577us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	68.577us	50	50	100.00
		aes_sideload	6.000s	63.910us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	119.904us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	119.904us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	119.904us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	119.904us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	119.904us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	68.577us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	68.577us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	229.151us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_cipher_fi	48.000s	20.761ms	308	350	88.00
		aes_ctr_fi	4.000s	453.751us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	229.151us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_cipher_fi	48.000s	20.761ms	308	350	88.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	48.000s	20.761ms	308	350	88.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	229.151us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_ctr_fi	4.000s	453.751us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_cipher_fi	48.000s	20.761ms	308	350	88.00
		aes_ctr_fi	4.000s	453.751us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	181.223us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_cipher_fi	48.000s	20.761ms	308	350	88.00
		aes_ctr_fi	4.000s	453.751us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_cipher_fi	48.000s	20.761ms	308	350	88.00
		aes_ctr_fi	4.000s	453.751us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_ctr_fi	4.000s	453.751us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	229.151us	50	50	100.00
		aes_control_fi	45.000s	65.650ms	283	300	94.33
		aes_cipher_fi	48.000s	20.761ms	308	350	88.00
V2S		TOTAL			920	985	93.40
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	7.050m	14.042ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1522	1602	95.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	5	71.43
V2	13	13	11	84.62
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	97.43	94.18	98.81	93.39	97.64	92.59	98.66	96.21

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 37 failures:
- Test aes_cipher_fi has 25 failures.
  - 11.aes_cipher_fi.71230703770195494011197579211192889341848204911811164869543657486021668108456
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job ID: smart:db05c5ba-45d0-488b-a0d3-9df8b8694aa4
```
  - 31.aes_cipher_fi.104714245950368651936995610881564204137772447218265152205784667847626302015875
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3cdbc4eb-6c5a-4ce0-bc5c-837665b40a66
```
  - ... and 23 more failures.
- Test aes_control_fi has 12 failures.
  - 94.aes_control_fi.105287835248065717516132130464086733863087016913296640652881500764450122405774
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/94.aes_control_fi/latest/run.log
```
  Job ID: smart:0ab482e7-9679-45c1-970e-54d8532a7723
```
  - 103.aes_control_fi.31784316995931979811892553568166284797958378297198885577429292498038788898628
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/103.aes_control_fi/latest/run.log
```
  Job ID: smart:41403b60-bd0c-41e3-829c-9065a550a093
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 17 failures:
- Test aes_cipher_fi has 17 failures.
  - 40.aes_cipher_fi.31157768061473675934594466476226399428010139614542910939528591129751933041634
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011315918 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011315918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 75.aes_cipher_fi.65577907328650799337654286567289234322738487910705951648523662073890817128892
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10014701265 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014701265 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 15 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 5 failures:

Test aes_stress_all_with_rand_reset has 5 failures.

0.aes_stress_all_with_rand_reset.62496063740524438799646972633983359388879433716445975541515418704594773573760
Line 777, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 373282826 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 373282826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.53282705643351136318903931758408541435649667772820447898281273072237353742850
Line 585, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2869053603 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2869053603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 16.aes_control_fi.91968399758675509606533094411546901537409170124813596348702357882991819878180
    Line 326, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011695513 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011695513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 124.aes_control_fi.47408450027346133708443493976008711987508383165930883266767965425437373373263
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/124.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007455970 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007455970 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 1.aes_core_fi.47876302974890211150305341250372142784427899682617145162763275081629071294562
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012444320 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012444320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.aes_core_fi.95203156721555208505400342011727842925790562967918736469277320564048792665008
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10021719200 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10021719200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.8411265384274609080684191777950393432131083257486374148495004359779685700534
Line 1141, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 325682219 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 325682219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.14031185687702097602980508535592353558796747587395354106921427534780362471064
Line 724, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14041914852 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 14041914852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=2) has 3 failures:
- Test aes_csr_aliasing has 1 failures.
  - 2.aes_csr_aliasing.83922171496205099333658867876302247687038017242867105080612409886610957589053
    Line 284, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_csr_aliasing/latest/run.log
```
  UVM_FATAL @ 10080965370 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xddc79384, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 10080965370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test aes_same_csr_outstanding has 2 failures.
  - 2.aes_same_csr_outstanding.111894204741876923789091647538308333781942685072504032180212365268309159427394
    Line 289, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10061432350 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0x25ae6484, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 10061432350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_same_csr_outstanding.77473110653651447852888440837927524810379877779732987777719271350790596565009
    Line 294, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_same_csr_outstanding/latest/run.log
```
  UVM_FATAL @ 10055570602 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.output_valid (addr=0xed688884, Comparison=CompareOpEq, exp_data=0x0, call_count=2)
  UVM_INFO @ 10055570602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:840) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_csr_mem_rw_with_rand_reset has 1 failures.
  - 3.aes_csr_mem_rw_with_rand_reset.17012831338441238552825576811844329439260030361974802770323285519815971537630
    Line 285, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 113832659 ps: (cip_base_vseq.sv:840) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 113832659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

6.aes_stress_all.101273780368967591265181953828150782839460977122418537366855771075064562735320
Line 51412, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 706395298 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 706360815 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 706395298 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 706360815 PS)
  UVM_ERROR @ 706395298 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (cip_base_vseq.sv:552) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.2151385976702505417817558990740515193997616943615661183700222499818889967148
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  38196906 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  38196906 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 53.aes_core_fi.29174159425170695544928493319790618048318927534976227561037544091010843471246
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10054784705 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xe4bddb84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10054784705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 65.aes_core_fi.66667800848663214282312066899076139745393312483905699483463221480420635719804
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016674016 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xc46f8084, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10016674016 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```