AES/UNMASKED Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	2.000s	86.816us	1	1	100.00
V1	smoke	aes_smoke	8.000s	110.647us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	62.958us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	51.289us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	289.772us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	70.439us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	157.915us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	51.289us	20	20	100.00
		aes_csr_aliasing	4.000s	70.439us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	110.647us	50	50	100.00
		aes_config_error	6.000s	170.150us	50	50	100.00
		aes_stress	8.000s	85.974us	50	50	100.00
V2	key_length	aes_smoke	8.000s	110.647us	50	50	100.00
		aes_config_error	6.000s	170.150us	50	50	100.00
		aes_stress	8.000s	85.974us	50	50	100.00
V2	back2back	aes_stress	8.000s	85.974us	50	50	100.00
		aes_b2b	9.000s	429.236us	50	50	100.00
V2	backpressure	aes_stress	8.000s	85.974us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	110.647us	50	50	100.00
		aes_config_error	6.000s	170.150us	50	50	100.00
		aes_stress	8.000s	85.974us	50	50	100.00
		aes_alert_reset	5.000s	628.774us	48	50	96.00
V2	failure_test	aes_man_cfg_err	8.000s	114.116us	50	50	100.00
		aes_config_error	6.000s	170.150us	50	50	100.00
		aes_alert_reset	5.000s	628.774us	48	50	96.00
V2	trigger_clear_test	aes_clear	5.000s	121.134us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	325.252us	1	1	100.00
V2	reset_recovery	aes_alert_reset	5.000s	628.774us	48	50	96.00
V2	stress	aes_stress	8.000s	85.974us	50	50	100.00
V2	sideload	aes_stress	8.000s	85.974us	50	50	100.00
		aes_sideload	9.000s	68.283us	50	50	100.00
V2	deinitialization	aes_deinit	5.000s	178.153us	50	50	100.00
V2	stress_all	aes_stress_all	34.000s	1.491ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	68.925us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	8.000s	3.322ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	8.000s	3.322ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	62.958us	5	5	100.00
		aes_csr_rw	4.000s	51.289us	20	20	100.00
		aes_csr_aliasing	4.000s	70.439us	5	5	100.00
		aes_same_csr_outstanding	4.000s	222.915us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	62.958us	5	5	100.00
		aes_csr_rw	4.000s	51.289us	20	20	100.00
		aes_csr_aliasing	4.000s	70.439us	5	5	100.00
		aes_same_csr_outstanding	4.000s	222.915us	20	20	100.00
V2		TOTAL			499	501	99.60
V2S	reseeding	aes_reseed	11.000s	435.615us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_cipher_fi	49.000s	78.761ms	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	112.440us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	112.440us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	112.440us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	112.440us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	260.237us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	2.009ms	5	5	100.00
		aes_tl_intg_err	8.000s	766.526us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	8.000s	766.526us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	5.000s	628.774us	48	50	96.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	112.440us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	110.647us	50	50	100.00
		aes_stress	8.000s	85.974us	50	50	100.00
		aes_alert_reset	5.000s	628.774us	48	50	96.00
		aes_core_fi	6.017m	10.016ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	112.440us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	51.233us	50	50	100.00
		aes_stress	8.000s	85.974us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	85.974us	50	50	100.00
		aes_sideload	9.000s	68.283us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	51.233us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	51.233us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	51.233us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	51.233us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	51.233us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	85.974us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	85.974us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	608.934us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_cipher_fi	49.000s	78.761ms	319	350	91.14
		aes_ctr_fi	4.000s	61.985us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	608.934us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_cipher_fi	49.000s	78.761ms	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	49.000s	78.761ms	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	608.934us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_ctr_fi	4.000s	61.985us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_cipher_fi	49.000s	78.761ms	319	350	91.14
		aes_ctr_fi	4.000s	61.985us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	5.000s	628.774us	48	50	96.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_cipher_fi	49.000s	78.761ms	319	350	91.14
		aes_ctr_fi	4.000s	61.985us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_cipher_fi	49.000s	78.761ms	319	350	91.14
		aes_ctr_fi	4.000s	61.985us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_ctr_fi	4.000s	61.985us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	608.934us	50	50	100.00
		aes_control_fi	44.000s	16.792ms	286	300	95.33
		aes_cipher_fi	49.000s	78.761ms	319	350	91.14
V2S		TOTAL			936	985	95.03
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	38.000s	1.646ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1541	1602	96.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.48	94.31	98.81	93.74	97.64	93.33	98.85	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_cipher_fi has 18 failures.
  - 0.aes_cipher_fi.44884758942043887840494607798953211915690212536095009678749691312253109598963
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_cipher_fi/latest/run.log
```
  Job ID: smart:9708d66a-99c9-450f-9ad1-588a2bd59bb5
```
  - 8.aes_cipher_fi.103126392622535088743361140442767005806404819348796294747363485180424025413140
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ac4633b4-3a1e-44bf-afff-c341c1443449
```
  - ... and 16 more failures.
- Test aes_control_fi has 6 failures.
  - 100.aes_control_fi.21921238542140938916635266092952438370601427386861716943912837788665893051130
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/100.aes_control_fi/latest/run.log
```
  Job ID: smart:e72ba7d7-d746-477a-a5b8-4f14dd6ab615
```
  - 205.aes_control_fi.65640116504318769585628838678295202246928088869753619831874706976643995853987
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/205.aes_control_fi/latest/run.log
```
  Job ID: smart:0b85f949-1b36-4a6e-afc9-8cfbd57711fb
```
  - ... and 4 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 31.aes_cipher_fi.75107164834620884663221388348040462217991350266749321904562243118998746626746
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006189369 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006189369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.aes_cipher_fi.34624707943206782927644780793934503944431066270503486273423539555645991426363
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010426846 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010426846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 90.aes_control_fi.7486223719598991638566159671958160347730831417018244043456980359242815679784
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/90.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007050225 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007050225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 93.aes_control_fi.99247967198473081144437351222665664286096742930742718965009162297208635536051
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/93.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10018377829 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018377829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.51766390168456749439159047793155238009218986994505316342751980396226110442623
Line 489, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2492815373 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2492815373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.111590547044063352287302391647652868708593966535234086615169207135093673900484
Line 877, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 728386313 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 728386313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.63766566353406309484955687735983077274671127517544448943522025311497609486481
Line 1214, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 580398842 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 580398842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.88649244762247706047896406323912541865374182812991272855993022226625548709906
Line 1104, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 462350306 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 462350306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 4.aes_core_fi.105774319063987052977766584996550827036199092988777845025161230564345878460131
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003978757 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003978757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 65.aes_core_fi.17206390902506960453160938916805902612539335246820653101582104834426624380755
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/65.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023477755 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023477755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_alert_reset has 1 failures.

1.aes_alert_reset.27587725337088682286005826725182379360319694560961705090406099181430925138823
Line 838, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_alert_reset/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 32009505 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 31967838 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 32009505 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 31967838 PS)
  UVM_ERROR @  32009505 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_ERROR (cip_base_vseq.sv:552) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.41774717250945598081501979264834528204361847125973011868197469136931818348348
    Line 414, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 173298177 ps: (cip_base_vseq.sv:552) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 173298177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd aes_reg_block.status (addr=*) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.65737847262447161382952035599291610886222131532133222264431368007329930076552
    Line 503, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 2251503902 ps: (csr_utils_pkg.sv:380) [csr_utils::csr_rd] Timeout waiting to csr_rd aes_reg_block.status (addr=0x59c36284)
  UVM_INFO @ 2251503902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:826) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.80954507295742255871501281456079735908649474692919510538561174019362726958542
    Line 1515, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1645924206 ps: (cip_base_vseq.sv:826) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 1645924206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*) == * has 1 failures:
- Test aes_core_fi has 1 failures.
  - 18.aes_core_fi.34329817005946143936829341826464276981161369751837247663153749834450253145965
    Line 312, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016316119 ps: (csr_utils_pkg.sv:577) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x978bac84) == 0x0
  UVM_INFO @ 10016316119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 33.aes_alert_reset.90426450276164190351671587319252629368061824614125026459531291125156718566806
    Line 533, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 4306981 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 4296777 PS)
  UVM_ERROR @   4306981 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   4306981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 33.aes_core_fi.78449953281296826230877654717051092078861934818352955891336023437084845572365
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10034349559 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034349559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_cipher_fi has 1 failures.
  - 52.aes_cipher_fi.29979893633487949831013252363874898682218097970173351030160297829315455508119
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```