AES/UNMASKED Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	70.299us	1	1	100.00
V1	smoke	aes_smoke	13.000s	75.418us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	231.629us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	183.809us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	8.000s	332.568us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	297.169us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	65.397us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	183.809us	20	20	100.00
		aes_csr_aliasing	4.000s	297.169us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	75.418us	50	50	100.00
		aes_config_error	9.000s	100.837us	50	50	100.00
		aes_stress	9.000s	65.988us	50	50	100.00
V2	key_length	aes_smoke	13.000s	75.418us	50	50	100.00
		aes_config_error	9.000s	100.837us	50	50	100.00
		aes_stress	9.000s	65.988us	50	50	100.00
V2	back2back	aes_stress	9.000s	65.988us	50	50	100.00
		aes_b2b	13.000s	379.004us	50	50	100.00
V2	backpressure	aes_stress	9.000s	65.988us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	75.418us	50	50	100.00
		aes_config_error	9.000s	100.837us	50	50	100.00
		aes_stress	9.000s	65.988us	50	50	100.00
		aes_alert_reset	9.000s	74.584us	49	50	98.00
V2	failure_test	aes_man_cfg_err	9.000s	55.051us	50	50	100.00
		aes_config_error	9.000s	100.837us	50	50	100.00
		aes_alert_reset	9.000s	74.584us	49	50	98.00
V2	trigger_clear_test	aes_clear	9.000s	81.378us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	859.993us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	74.584us	49	50	98.00
V2	stress	aes_stress	9.000s	65.988us	50	50	100.00
V2	sideload	aes_stress	9.000s	65.988us	50	50	100.00
		aes_sideload	10.000s	89.126us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	118.809us	50	50	100.00
V2	stress_all	aes_stress_all	30.000s	892.155us	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	52.609us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	266.360us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	266.360us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	231.629us	5	5	100.00
		aes_csr_rw	3.000s	183.809us	20	20	100.00
		aes_csr_aliasing	4.000s	297.169us	5	5	100.00
		aes_same_csr_outstanding	4.000s	165.293us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	231.629us	5	5	100.00
		aes_csr_rw	3.000s	183.809us	20	20	100.00
		aes_csr_aliasing	4.000s	297.169us	5	5	100.00
		aes_same_csr_outstanding	4.000s	165.293us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	11.000s	182.270us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_cipher_fi	47.000s	10.003ms	319	350	91.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	3.000s	71.131us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	3.000s	71.131us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	3.000s	71.131us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	3.000s	71.131us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	181.564us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	445.770us	5	5	100.00
		aes_tl_intg_err	6.000s	1.813ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	1.813ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	74.584us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	3.000s	71.131us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	75.418us	50	50	100.00
		aes_stress	9.000s	65.988us	50	50	100.00
		aes_alert_reset	9.000s	74.584us	49	50	98.00
		aes_core_fi	19.000s	10.034ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	3.000s	71.131us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	149.555us	50	50	100.00
		aes_stress	9.000s	65.988us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	9.000s	65.988us	50	50	100.00
		aes_sideload	10.000s	89.126us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	149.555us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	149.555us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	149.555us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	149.555us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	149.555us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	9.000s	65.988us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	9.000s	65.988us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	109.559us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_cipher_fi	47.000s	10.003ms	319	350	91.14
		aes_ctr_fi	14.000s	59.911us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	109.559us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_cipher_fi	47.000s	10.003ms	319	350	91.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.003ms	319	350	91.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	109.559us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_ctr_fi	14.000s	59.911us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_cipher_fi	47.000s	10.003ms	319	350	91.14
		aes_ctr_fi	14.000s	59.911us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	74.584us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_cipher_fi	47.000s	10.003ms	319	350	91.14
		aes_ctr_fi	14.000s	59.911us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_cipher_fi	47.000s	10.003ms	319	350	91.14
		aes_ctr_fi	14.000s	59.911us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_ctr_fi	14.000s	59.911us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	109.559us	49	50	98.00
		aes_control_fi	44.000s	15.785ms	273	300	91.00
		aes_cipher_fi	47.000s	10.003ms	319	350	91.14
V2S		TOTAL			923	985	93.71
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.900m	13.000ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1529	1602	95.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.11	97.46	94.26	98.75	93.57	97.72	91.11	98.85	95.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
- Test aes_control_fi has 17 failures.
  - 20.aes_control_fi.92191931362968663466556135279455619568470679989844217541691752650748321106238
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:1bac1f5e-1b8e-425f-9be6-e9787482f1f2
```
  - 23.aes_control_fi.113164077814054827109338536628088646288706443205954417299463676159377480831192
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job ID: smart:fe6f3565-e2ed-4f48-bc53-35cbe56cef53
```
  - ... and 15 more failures.
- Test aes_cipher_fi has 16 failures.
  - 91.aes_cipher_fi.4739808546911630546943720079310310866626482325591617925559489225487222029559
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/91.aes_cipher_fi/latest/run.log
```
  Job ID: smart:583ff09f-ae7a-47bc-8dc3-4fba92863136
```
  - 97.aes_cipher_fi.62638880388560186978663495099107775064569421685061422125309526459063754277833
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/97.aes_cipher_fi/latest/run.log
```
  Job ID: smart:2a208107-a2e6-4b2b-acab-945e28e21438
```
  - ... and 14 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_cipher_fi has 15 failures.
  - 1.aes_cipher_fi.5860185432281699788422498341679487929639951770003051888039316863784007602118
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010454550 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010454550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.aes_cipher_fi.115269509101497238968746621223015824357418872911389378635479468127555393769425
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011745940 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011745940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 6.aes_control_fi.76269380400187204023519301955480240355465896710811168163462305314485790463967
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022938813 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022938813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_control_fi.111534260062618669852780174735139388991183747299776643881968628089926456380401
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10005986636 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005986636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.104826601132474113596518586888204872359043715347724316306935757020699601266635
Line 1317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 734870449 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 734870449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.27417258973257745178445040163465384869148179783640342996394373304449023551381
Line 1094, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 844448572 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 844448572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

1.aes_stress_all_with_rand_reset.52945632648769442768421351272967776588338275684798219200551898601522343110348
Line 508, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 396376227 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 396376227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.12870602532312167076007076438965889303125887524155870633963406225939959426464
Line 582, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 497219419 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 497219419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 14.aes_core_fi.67983190859588267074969678927811046190882624105473673060803432175294586493694
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/14.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016486204 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016486204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.aes_core_fi.1593510235353020488488940553734156517286709511195510383521150318044866246224
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10033890910 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033890910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 2.aes_alert_reset.111535198680138195788732599291292094063289530907355113756273474285456228407741
    Line 4307, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 46813164 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 46771497 PS)
  UVM_ERROR @  46813164 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  46813164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 30.aes_fi.76440224047960268344015866129743614536274105985917790658860044847377672016698
    Line 10611, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_fi/latest/run.log
```
  UVM_FATAL @ 109559269 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 109559269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```