AES/UNMASKED Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	60.203us	1	1	100.00
V1	smoke	aes_smoke	13.000s	57.866us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	176.617us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	85.942us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	327.635us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	244.958us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	3.000s	67.342us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	85.942us	20	20	100.00
		aes_csr_aliasing	5.000s	244.958us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	57.866us	50	50	100.00
		aes_config_error	24.000s	110.934us	50	50	100.00
		aes_stress	13.000s	106.564us	50	50	100.00
V2	key_length	aes_smoke	13.000s	57.866us	50	50	100.00
		aes_config_error	24.000s	110.934us	50	50	100.00
		aes_stress	13.000s	106.564us	50	50	100.00
V2	back2back	aes_stress	13.000s	106.564us	50	50	100.00
		aes_b2b	17.000s	655.899us	50	50	100.00
V2	backpressure	aes_stress	13.000s	106.564us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	57.866us	50	50	100.00
		aes_config_error	24.000s	110.934us	50	50	100.00
		aes_stress	13.000s	106.564us	50	50	100.00
		aes_alert_reset	19.000s	63.820us	50	50	100.00
V2	failure_test	aes_man_cfg_err	18.000s	65.442us	50	50	100.00
		aes_config_error	24.000s	110.934us	50	50	100.00
		aes_alert_reset	19.000s	63.820us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	68.598us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	667.841us	1	1	100.00
V2	reset_recovery	aes_alert_reset	19.000s	63.820us	50	50	100.00
V2	stress	aes_stress	13.000s	106.564us	50	50	100.00
V2	sideload	aes_stress	13.000s	106.564us	50	50	100.00
		aes_sideload	9.000s	103.081us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	85.341us	50	50	100.00
V2	stress_all	aes_stress_all	23.000s	397.308us	10	10	100.00
V2	alert_test	aes_alert_test	9.000s	59.224us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	10.000s	262.330us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	10.000s	262.330us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	176.617us	5	5	100.00
		aes_csr_rw	3.000s	85.942us	20	20	100.00
		aes_csr_aliasing	5.000s	244.958us	5	5	100.00
		aes_same_csr_outstanding	8.000s	240.601us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	176.617us	5	5	100.00
		aes_csr_rw	3.000s	85.942us	20	20	100.00
		aes_csr_aliasing	5.000s	244.958us	5	5	100.00
		aes_same_csr_outstanding	8.000s	240.601us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	10.000s	1.268ms	50	50	100.00
V2S	fault_inject	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_cipher_fi	51.000s	15.789ms	328	350	93.71
V2S	shadow_reg_update_error	aes_shadow_reg_errors	8.000s	355.986us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	8.000s	355.986us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	8.000s	355.986us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	8.000s	355.986us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	452.866us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.033ms	5	5	100.00
		aes_tl_intg_err	5.000s	1.138ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	1.138ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	19.000s	63.820us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	8.000s	355.986us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	57.866us	50	50	100.00
		aes_stress	13.000s	106.564us	50	50	100.00
		aes_alert_reset	19.000s	63.820us	50	50	100.00
		aes_core_fi	6.433m	10.010ms	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	8.000s	355.986us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	65.568us	50	50	100.00
		aes_stress	13.000s	106.564us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	13.000s	106.564us	50	50	100.00
		aes_sideload	9.000s	103.081us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	65.568us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	65.568us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	65.568us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	65.568us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	65.568us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	13.000s	106.564us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	13.000s	106.564us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	21.000s	278.435us	48	50	96.00
V2S	sec_cm_main_fsm_redun	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_cipher_fi	51.000s	15.789ms	328	350	93.71
		aes_ctr_fi	8.000s	123.376us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	21.000s	278.435us	48	50	96.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_cipher_fi	51.000s	15.789ms	328	350	93.71
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	15.789ms	328	350	93.71
V2S	sec_cm_ctr_fsm_sparse	aes_fi	21.000s	278.435us	48	50	96.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_ctr_fi	8.000s	123.376us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_cipher_fi	51.000s	15.789ms	328	350	93.71
		aes_ctr_fi	8.000s	123.376us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	19.000s	63.820us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_cipher_fi	51.000s	15.789ms	328	350	93.71
		aes_ctr_fi	8.000s	123.376us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_cipher_fi	51.000s	15.789ms	328	350	93.71
		aes_ctr_fi	8.000s	123.376us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_ctr_fi	8.000s	123.376us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	21.000s	278.435us	48	50	96.00
		aes_control_fi	49.000s	32.843ms	273	300	91.00
		aes_cipher_fi	51.000s	15.789ms	328	350	93.71
V2S		TOTAL			927	985	94.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	21.300m	82.629ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.46	94.26	98.81	93.48	97.72	92.59	98.85	97.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_control_fi has 15 failures.
  - 12.aes_control_fi.111241986817846932452240306753769428837362944506656921544795894850821876680873
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:e7f64785-2615-417b-8788-cd6378fa5ba1
```
  - 24.aes_control_fi.26221068180405098102931226885087065476076236927087709950594670310813156691610
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  Job ID: smart:824057a5-0536-4bc0-8400-bbabbf673485
```
  - ... and 13 more failures.
- Test aes_cipher_fi has 14 failures.
  - 42.aes_cipher_fi.80738839290040410206239307745777334390667935402417322532321015945183393356416
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/42.aes_cipher_fi/latest/run.log
```
  Job ID: smart:ad1dbd6d-7011-4462-a22a-0f3281a82aa9
```
  - 59.aes_cipher_fi.106980624039936753818892506592686843576813273568710800397287917651874206424895
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/59.aes_cipher_fi/latest/run.log
```
  Job ID: smart:b63d9227-adeb-4bf7-b645-01bf1e54573b
```
  - ... and 12 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_control_fi has 12 failures.
  - 4.aes_control_fi.12758042891703004925808850727933458096386898011843212792583692049509257746280
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10075295172 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10075295172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_control_fi.64365382095940448229861529188617096456349648396669980800949358451614037549359
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10011948478 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011948478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_cipher_fi has 8 failures.
  - 20.aes_cipher_fi.39405876442246561592263334455010876190658167303803054880363539364648732681989
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010735616 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010735616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_cipher_fi.66959673117406246189604604301333010577452653049329973088559946786312505404024
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009084723 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009084723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

3.aes_stress_all_with_rand_reset.99902450281882836039862323797982395702280003856247850924852045647190609620773
Line 1541, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4659793426 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4659793426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.aes_stress_all_with_rand_reset.53041025257963226904476142526779516256470357792735099996241824973530906534739
Line 854, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 788789852 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 788789852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 1.aes_core_fi.108041376507309475171768253727558370626473417966751178224979921558632388680976
    Line 322, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013609466 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013609466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.aes_core_fi.82013876157490137962546104744709582957620786730213282343284412736349998838986
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003507813 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003507813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

0.aes_stress_all_with_rand_reset.34511341489611184136212990405073334377600027351212046611629546836404409060732
Line 1523, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14664821043 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 14664821043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.85743698435595213008719449667361766101815997851281259671858185512481341111687
Line 1514, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1645699334 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1645699334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 24.aes_core_fi.24219123545095988395510374706052237067724485120806902835187280682943884526312
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011631874 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011631874 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 63.aes_core_fi.26277660293559894681722529180336679464586913367086769915047838407087519150664
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015612702 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015612702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:549) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.5142399566006173325688135077262776561180724648208864358235066500681143752579
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  47141502 ps: (cip_base_vseq.sv:549) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  47141502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 3.aes_fi.31221805404145444830967255728595182093828555759620018680001277474388441358215
    Line 1158, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 22358441 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 22312986 PS)
  UVM_ERROR @  22358441 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  22358441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 37.aes_core_fi.108774854633647518848347962459930473179106757513077318199058764707576290439386
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010218455 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x92853d84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10010218455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 41.aes_fi.34532868744259188348854768123845137344340443440687314662939609004836377196907
    Line 4505, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_fi/latest/run.log
```
  UVM_FATAL @  24395748 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @  24395748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```