AES/UNMASKED Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	71.175us	1	1	100.00
V1	smoke	aes_smoke	10.000s	142.861us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	74.506us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	126.874us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	194.518us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	132.991us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	80.615us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	126.874us	20	20	100.00
		aes_csr_aliasing	5.000s	132.991us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	10.000s	142.861us	50	50	100.00
		aes_config_error	9.000s	85.919us	50	50	100.00
		aes_stress	8.000s	360.412us	50	50	100.00
V2	key_length	aes_smoke	10.000s	142.861us	50	50	100.00
		aes_config_error	9.000s	85.919us	50	50	100.00
		aes_stress	8.000s	360.412us	50	50	100.00
V2	back2back	aes_stress	8.000s	360.412us	50	50	100.00
		aes_b2b	11.000s	439.840us	50	50	100.00
V2	backpressure	aes_stress	8.000s	360.412us	50	50	100.00
V2	multi_message	aes_smoke	10.000s	142.861us	50	50	100.00
		aes_config_error	9.000s	85.919us	50	50	100.00
		aes_stress	8.000s	360.412us	50	50	100.00
		aes_alert_reset	9.000s	85.071us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	129.272us	50	50	100.00
		aes_config_error	9.000s	85.919us	50	50	100.00
		aes_alert_reset	9.000s	85.071us	50	50	100.00
V2	trigger_clear_test	aes_clear	15.000s	117.872us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	167.589us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	85.071us	50	50	100.00
V2	stress	aes_stress	8.000s	360.412us	50	50	100.00
V2	sideload	aes_stress	8.000s	360.412us	50	50	100.00
		aes_sideload	9.000s	60.241us	50	50	100.00
V2	deinitialization	aes_deinit	8.000s	57.444us	50	50	100.00
V2	stress_all	aes_stress_all	31.000s	4.386ms	10	10	100.00
V2	alert_test	aes_alert_test	7.000s	66.774us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	1.391ms	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	1.391ms	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	74.506us	5	5	100.00
		aes_csr_rw	4.000s	126.874us	20	20	100.00
		aes_csr_aliasing	5.000s	132.991us	5	5	100.00
		aes_same_csr_outstanding	4.000s	153.425us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	74.506us	5	5	100.00
		aes_csr_rw	4.000s	126.874us	20	20	100.00
		aes_csr_aliasing	5.000s	132.991us	5	5	100.00
		aes_same_csr_outstanding	4.000s	153.425us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	19.000s	61.927us	50	50	100.00
V2S	fault_inject	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_cipher_fi	51.000s	32.169ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	108.525us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	108.525us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	108.525us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	108.525us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	159.117us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	5.000s	1.427ms	5	5	100.00
		aes_tl_intg_err	6.000s	529.043us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	529.043us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	85.071us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	108.525us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	10.000s	142.861us	50	50	100.00
		aes_stress	8.000s	360.412us	50	50	100.00
		aes_alert_reset	9.000s	85.071us	50	50	100.00
		aes_core_fi	1.050m	10.065ms	64	70	91.43
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	108.525us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	370.343us	50	50	100.00
		aes_stress	8.000s	360.412us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	360.412us	50	50	100.00
		aes_sideload	9.000s	60.241us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	370.343us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	370.343us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	370.343us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	370.343us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	370.343us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	360.412us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	360.412us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	5.000s	303.709us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_cipher_fi	51.000s	32.169ms	325	350	92.86
		aes_ctr_fi	8.000s	65.824us	48	50	96.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	5.000s	303.709us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_cipher_fi	51.000s	32.169ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	32.169ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	5.000s	303.709us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_ctr_fi	8.000s	65.824us	48	50	96.00
V2S	sec_cm_ctrl_sparse	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_cipher_fi	51.000s	32.169ms	325	350	92.86
		aes_ctr_fi	8.000s	65.824us	48	50	96.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	85.071us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_cipher_fi	51.000s	32.169ms	325	350	92.86
		aes_ctr_fi	8.000s	65.824us	48	50	96.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_cipher_fi	51.000s	32.169ms	325	350	92.86
		aes_ctr_fi	8.000s	65.824us	48	50	96.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_ctr_fi	8.000s	65.824us	48	50	96.00
V2S	sec_cm_data_reg_local_esc	aes_fi	5.000s	303.709us	49	50	98.00
		aes_control_fi	42.000s	16.279ms	283	300	94.33
		aes_cipher_fi	51.000s	32.169ms	325	350	92.86
V2S		TOTAL			934	985	94.82
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.900m	47.389ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1541	1602	96.19

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.46	94.26	98.77	93.65	97.72	93.33	98.85	96.81

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 29 failures:
- Test aes_control_fi has 13 failures.
  - 3.aes_control_fi.47826943548657903163407202926668618449051936298611160389953409100946331014784
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job ID: smart:7ff19fec-4a42-40e1-9a85-46f0cf196cb7
```
  - 13.aes_control_fi.71413987658451031578213068875738500038161264700233075260407364834220937167571
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job ID: smart:8e1bfe7a-86b5-4c72-877e-25632bdbf013
```
  - ... and 11 more failures.
- Test aes_ctr_fi has 2 failures.
  - 8.aes_ctr_fi.30321339389408454506753024266358794157440410119840686754527717326860066143035
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_ctr_fi/latest/run.log
```
  Job ID: smart:b707ed9a-817a-46df-aa9e-b6b9159eb691
```
  - 29.aes_ctr_fi.36686636191185413716197551435791761014696643914306137276791562972435078229458
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/29.aes_ctr_fi/latest/run.log
```
  Job ID: smart:4b089d33-7fbb-4fce-8e97-693eade55b89
```
- Test aes_cipher_fi has 14 failures.
  - 31.aes_cipher_fi.103932469464836641737787819229631547266461905727770921363393287272990557210875
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d81a9417-7ff2-4962-b0f6-cb4114cdb396
```
  - 36.aes_cipher_fi.113187047506618474042409655930708616713003980873271592719830282251806536107101
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  Job ID: smart:566876f0-ccf6-44eb-9023-d519e8bf3f6f
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_cipher_fi has 11 failures.
  - 9.aes_cipher_fi.35328354410891414483831925030127051885057879630856237923556274492158300780072
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10013884138 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013884138 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.aes_cipher_fi.44427077844646454379769187639327338078282988131808886516792314724429198758128
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/16.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005436270 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005436270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.12323828493493513031579521353753181040427825628766227157252410162041625428674
Line 1200, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 323562527 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 323562527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.43397866622234588302528140461516546970540955141638377466299234454986529111018
Line 808, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 706548170 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 706548170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 11.aes_core_fi.58360918847015306421210939312288006482821451751591300985218090505621652585956
    Line 323, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10004313863 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004313863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.aes_core_fi.83695384614062679826814983717972617128314461366344144978303151008047620980302
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008347336 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008347336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_control_fi has 4 failures.
  - 119.aes_control_fi.24829840601679812984824763802199409874278733243761836785060136121468860834354
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/119.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10012650626 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012650626 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 157.aes_control_fi.82332687525043586715983270886144809222069852433167214532826592785990521904275
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/157.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004296852 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004296852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.32594999630245919953206981523694711088345286789183346108802536090199538635842
    Line 910, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 221236418 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 221236418 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 18.aes_core_fi.63275593626088373080309462367146783517701455700368884765624620337915737276135
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10065441345 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xb7f60384, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10065441345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_fi has 1 failures.
  - 37.aes_fi.17802791292512573002842249379138925259210404386847981686671882372240626971168
    Line 3415, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/37.aes_fi/latest/run.log
```
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 14543059 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 14527186 PS)
  UVM_ERROR @  14543059 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  14543059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```