AES/UNMASKED Simulation Results

Monday August 05 2024 23:02:13 UTC

GitHub Revision: `e4c5daa580`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 57478527486894479494471273459769404654835266620222125964939301612221385668501

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	82.124us	1	1	100.00
V1	smoke	aes_smoke	13.000s	148.730us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	77.567us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	51.805us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	1.746ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	108.589us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	23.000s	152.222us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	51.805us	20	20	100.00
		aes_csr_aliasing	8.000s	108.589us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	148.730us	50	50	100.00
		aes_config_error	14.000s	230.404us	50	50	100.00
		aes_stress	10.000s	89.106us	50	50	100.00
V2	key_length	aes_smoke	13.000s	148.730us	50	50	100.00
		aes_config_error	14.000s	230.404us	50	50	100.00
		aes_stress	10.000s	89.106us	50	50	100.00
V2	back2back	aes_stress	10.000s	89.106us	50	50	100.00
		aes_b2b	16.000s	135.968us	50	50	100.00
V2	backpressure	aes_stress	10.000s	89.106us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	148.730us	50	50	100.00
		aes_config_error	14.000s	230.404us	50	50	100.00
		aes_stress	10.000s	89.106us	50	50	100.00
		aes_alert_reset	9.000s	373.608us	50	50	100.00
V2	failure_test	aes_man_cfg_err	11.000s	90.750us	50	50	100.00
		aes_config_error	14.000s	230.404us	50	50	100.00
		aes_alert_reset	9.000s	373.608us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	212.021us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	319.406us	1	1	100.00
V2	reset_recovery	aes_alert_reset	9.000s	373.608us	50	50	100.00
V2	stress	aes_stress	10.000s	89.106us	50	50	100.00
V2	sideload	aes_stress	10.000s	89.106us	50	50	100.00
		aes_sideload	9.000s	55.290us	50	50	100.00
V2	deinitialization	aes_deinit	18.000s	80.429us	50	50	100.00
V2	stress_all	aes_stress_all	28.000s	956.485us	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	52.877us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	9.000s	129.813us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	9.000s	129.813us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	77.567us	5	5	100.00
		aes_csr_rw	4.000s	51.805us	20	20	100.00
		aes_csr_aliasing	8.000s	108.589us	5	5	100.00
		aes_same_csr_outstanding	12.000s	107.301us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	77.567us	5	5	100.00
		aes_csr_rw	4.000s	51.805us	20	20	100.00
		aes_csr_aliasing	8.000s	108.589us	5	5	100.00
		aes_same_csr_outstanding	12.000s	107.301us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	13.000s	58.240us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_cipher_fi	52.000s	24.262ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	259.633us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	259.633us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	259.633us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	259.633us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	238.068us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	8.000s	690.061us	5	5	100.00
		aes_tl_intg_err	10.000s	483.665us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	10.000s	483.665us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	9.000s	373.608us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	259.633us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	148.730us	50	50	100.00
		aes_stress	10.000s	89.106us	50	50	100.00
		aes_alert_reset	9.000s	373.608us	50	50	100.00
		aes_core_fi	6.167m	10.013ms	62	70	88.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	259.633us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	8.000s	61.750us	50	50	100.00
		aes_stress	10.000s	89.106us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	10.000s	89.106us	50	50	100.00
		aes_sideload	9.000s	55.290us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	8.000s	61.750us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	8.000s	61.750us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	8.000s	61.750us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	8.000s	61.750us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	8.000s	61.750us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	10.000s	89.106us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	10.000s	89.106us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	69.091us	46	50	92.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_cipher_fi	52.000s	24.262ms	326	350	93.14
		aes_ctr_fi	12.000s	98.713us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	69.091us	46	50	92.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_cipher_fi	52.000s	24.262ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	52.000s	24.262ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	69.091us	46	50	92.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_ctr_fi	12.000s	98.713us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_cipher_fi	52.000s	24.262ms	326	350	93.14
		aes_ctr_fi	12.000s	98.713us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	9.000s	373.608us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_cipher_fi	52.000s	24.262ms	326	350	93.14
		aes_ctr_fi	12.000s	98.713us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_cipher_fi	52.000s	24.262ms	326	350	93.14
		aes_ctr_fi	12.000s	98.713us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_ctr_fi	12.000s	98.713us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	69.091us	46	50	92.00
		aes_control_fi	49.000s	10.005ms	277	300	92.33
		aes_cipher_fi	52.000s	24.262ms	326	350	93.14
V2S		TOTAL			926	985	94.01
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.017m	6.012ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1533	1602	95.69

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.10	97.43	94.18	98.77	93.42	97.64	91.11	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 24 failures:
- Test aes_control_fi has 12 failures.
  - 7.aes_control_fi.96745189782676586336895395990215594174535674815387922873797015718607517368292
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job ID: smart:836a1362-0e33-42bb-b67c-f943c1a4a462
```
  - 63.aes_control_fi.29527401882282721238716469593047525952902913841502343850251491901466522034933
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/63.aes_control_fi/latest/run.log
```
  Job ID: smart:cef62460-3b39-46ad-9c65-71c4b7248686
```
  - ... and 10 more failures.
- Test aes_cipher_fi has 12 failures.
  - 19.aes_cipher_fi.113117685606781135418565784145017756310846661362021205217654052165447415806125
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/19.aes_cipher_fi/latest/run.log
```
  Job ID: smart:d221b602-0197-496b-ac24-10d3e3b3a567
```
  - 76.aes_cipher_fi.22801626353059773560293738320397988692603909951478196944790802170253403629381
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5d7b162d-77e3-47a1-89b4-37da3f2c4eea
```
  - ... and 10 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 56.aes_cipher_fi.35962390775701971530188969993705671388649086891360663245583261388585776292688
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005345865 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005345865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 150.aes_cipher_fi.52516691431238500647308256574807422516156171874018527679682758307726780822474
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/150.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003894368 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003894368 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 23.aes_control_fi.56423507045755553047717287002543015541548929786606441971800531654128028720061
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10007086740 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007086740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_control_fi.3127858882331965865764964414956890553682572573149296383066860467873002776822
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006068497 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006068497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.76780047588719806802840161928973353533640360841405637707233246825024608587258
Line 529, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4494621837 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 4494621837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.15916458207219575020487397702785750542342056855668103212179361479947110845810
Line 1847, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 500168865 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 500168865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 11.aes_core_fi.46701274800581736542360575369906089026834646330732476967561643369327609661262
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006740962 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006740962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 41.aes_core_fi.98320321936709581923460054114202157240386561441321108348000554883111203401185
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/41.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007182249 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007182249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 3 failures:

Test aes_stress_all_with_rand_reset has 3 failures.

4.aes_stress_all_with_rand_reset.86738054897413302313379086053161483799164045480304872245426848271393503907512
Line 1092, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 270602248 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 270602248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aes_stress_all_with_rand_reset.29838418617709456661475268203851155269272015851742908529753860092376234543905
Line 1905, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2283999568 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2283999568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 2 failures:

Test aes_fi has 2 failures.

20.aes_fi.62397883764338757889036518192125552145161059124838624158306946613700832020140
Line 8817, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_fi/latest/run.log

  UVM_FATAL @ 315739287 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 315739287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aes_fi.64792140145495260742647651880554323855399418439438558471112603182827093423513
Line 15055, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/30.aes_fi/latest/run.log

  UVM_FATAL @ 154850217 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 154850217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Exit reason: Error: User command failed xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 2 failures:

Test aes_fi has 2 failures.

23.aes_fi.22838730060056249690010269178296593720268063881763373801624794464264210051946
Line 2844, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/23.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 67284911 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 67194002 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 67284911 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 67194002 PS)
  UVM_ERROR @  67284911 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

33.aes_fi.16670985778925318233667543116036567184652783043799928627078234694078530095404
Line 4011, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/33.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 149037344 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 148894487 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspace/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 149037344 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 148894487 PS)
  UVM_ERROR @ 149037344 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 38.aes_core_fi.10309034111278423954398055246341644509180184955795423548484664483299511626516
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/38.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012399780 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012399780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 53.aes_core_fi.15979947486402869521332998465062717827035187840771084373627994153231937160642
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/53.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10023090142 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10023090142 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:549) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 3.aes_stress_all_with_rand_reset.59130403910770182660972724254139694379545016573998276120239063758584024546667
    Line 1414, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 405116105 ps: (cip_base_vseq.sv:549) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 405116105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 25.aes_core_fi.115430329887808096657031091887438230556088652543870570475706651765608373299606
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012766228 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x7863ca84, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10012766228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```