AES/UNMASKED Simulation Results

Friday August 02 2024 23:02:48 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 75989420798843487383163268541581889763599806834398027919895759109584083292465

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	8.000s	56.398us	1	1	100.00
V1	smoke	aes_smoke	13.000s	63.325us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	95.300us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	55.811us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	9.000s	321.028us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	93.653us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	100.731us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	55.811us	20	20	100.00
		aes_csr_aliasing	5.000s	93.653us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	13.000s	63.325us	50	50	100.00
		aes_config_error	14.000s	80.124us	50	50	100.00
		aes_stress	14.000s	61.703us	50	50	100.00
V2	key_length	aes_smoke	13.000s	63.325us	50	50	100.00
		aes_config_error	14.000s	80.124us	50	50	100.00
		aes_stress	14.000s	61.703us	50	50	100.00
V2	back2back	aes_stress	14.000s	61.703us	50	50	100.00
		aes_b2b	16.000s	492.017us	50	50	100.00
V2	backpressure	aes_stress	14.000s	61.703us	50	50	100.00
V2	multi_message	aes_smoke	13.000s	63.325us	50	50	100.00
		aes_config_error	14.000s	80.124us	50	50	100.00
		aes_stress	14.000s	61.703us	50	50	100.00
		aes_alert_reset	20.000s	156.094us	50	50	100.00
V2	failure_test	aes_man_cfg_err	14.000s	71.676us	50	50	100.00
		aes_config_error	14.000s	80.124us	50	50	100.00
		aes_alert_reset	20.000s	156.094us	50	50	100.00
V2	trigger_clear_test	aes_clear	14.000s	109.685us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	126.892us	1	1	100.00
V2	reset_recovery	aes_alert_reset	20.000s	156.094us	50	50	100.00
V2	stress	aes_stress	14.000s	61.703us	50	50	100.00
V2	sideload	aes_stress	14.000s	61.703us	50	50	100.00
		aes_sideload	9.000s	235.794us	50	50	100.00
V2	deinitialization	aes_deinit	14.000s	63.333us	50	50	100.00
V2	stress_all	aes_stress_all	29.000s	352.578us	10	10	100.00
V2	alert_test	aes_alert_test	13.000s	56.195us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	189.020us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	189.020us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	95.300us	5	5	100.00
		aes_csr_rw	4.000s	55.811us	20	20	100.00
		aes_csr_aliasing	5.000s	93.653us	5	5	100.00
		aes_same_csr_outstanding	5.000s	94.331us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	95.300us	5	5	100.00
		aes_csr_rw	4.000s	55.811us	20	20	100.00
		aes_csr_aliasing	5.000s	93.653us	5	5	100.00
		aes_same_csr_outstanding	5.000s	94.331us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	14.000s	118.520us	50	50	100.00
V2S	fault_inject	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_cipher_fi	51.000s	10.002ms	323	350	92.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	95.746us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	95.746us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	95.746us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	95.746us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	8.000s	132.647us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	12.000s	3.007ms	5	5	100.00
		aes_tl_intg_err	5.000s	485.945us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	485.945us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	20.000s	156.094us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	95.746us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	13.000s	63.325us	50	50	100.00
		aes_stress	14.000s	61.703us	50	50	100.00
		aes_alert_reset	20.000s	156.094us	50	50	100.00
		aes_core_fi	49.000s	10.060ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	95.746us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	13.000s	59.733us	50	50	100.00
		aes_stress	14.000s	61.703us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	14.000s	61.703us	50	50	100.00
		aes_sideload	9.000s	235.794us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	13.000s	59.733us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	13.000s	59.733us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	13.000s	59.733us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	13.000s	59.733us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	13.000s	59.733us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	14.000s	61.703us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	14.000s	61.703us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	10.000s	167.759us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_cipher_fi	51.000s	10.002ms	323	350	92.29
		aes_ctr_fi	9.000s	102.507us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	10.000s	167.759us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_cipher_fi	51.000s	10.002ms	323	350	92.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	10.002ms	323	350	92.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	10.000s	167.759us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_ctr_fi	9.000s	102.507us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_cipher_fi	51.000s	10.002ms	323	350	92.29
		aes_ctr_fi	9.000s	102.507us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	20.000s	156.094us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_cipher_fi	51.000s	10.002ms	323	350	92.29
		aes_ctr_fi	9.000s	102.507us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_cipher_fi	51.000s	10.002ms	323	350	92.29
		aes_ctr_fi	9.000s	102.507us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_ctr_fi	9.000s	102.507us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	10.000s	167.759us	50	50	100.00
		aes_control_fi	50.000s	10.005ms	266	300	88.67
		aes_cipher_fi	51.000s	10.002ms	323	350	92.29
V2S		TOTAL			919	985	93.30
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.333m	12.954ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1526	1602	95.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.55	94.48	98.81	93.74	97.72	93.33	98.85	96.01

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 28 failures:
- Test aes_control_fi has 16 failures.
  - 15.aes_control_fi.82268594113977456183681880498658492621386328680476281185182075115943077324325
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job ID: smart:aebf4187-44ae-4027-ab55-e3dbc1f7c4f1
```
  - 20.aes_control_fi.10229975898715861139634158047176533725696622791648476602633505475279970680489
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  Job ID: smart:4c1311f4-323a-471e-a5c6-f06d969a5abc
```
  - ... and 14 more failures.
- Test aes_cipher_fi has 12 failures.
  - 64.aes_cipher_fi.29778433287130867787567870080195326529402056012266806478992382604087606189342
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/64.aes_cipher_fi/latest/run.log
```
  Job ID: smart:3588177a-52a7-4378-b3a3-e424f0e3bc5f
```
  - 75.aes_cipher_fi.14702595364311705198155395155871363577685165595936154117447555033276736309443
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/75.aes_cipher_fi/latest/run.log
```
  Job ID: smart:c4924e12-590e-48e9-a3f6-08bd03270a57
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 18 failures:
- Test aes_control_fi has 18 failures.
  - 35.aes_control_fi.107710580534450228109594084761857615021363165577290677533031976994265222527422
    Line 318, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/35.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10034760347 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10034760347 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_control_fi.79755862182604060589093866310354960967686252583298680808431814105817739268914
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016032849 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016032849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 16 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_cipher_fi has 15 failures.
  - 36.aes_cipher_fi.517393242215566161830950533773827165094536054066680249227117106501108553904
    Line 325, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/36.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003636441 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003636441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 49.aes_cipher_fi.76906506098859942069885535293913517894215645402280064477165820800714596284480
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/49.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007968593 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007968593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.111489365778517297418799932828447895562559521382598865447243518703082650415044
Line 941, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 471502283 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 471502283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.53394430887963824707392735658040451193186954123841592421654586635526495086156
Line 1140, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 606949560 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 606949560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 15.aes_core_fi.87007151552733762575787305101505992039226227688528728052161757737500507908494
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/15.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006380268 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006380268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 22.aes_core_fi.98621133685288980399609293890801711967656212549038854350184680192290886494828
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022259616 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022259616 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 2 failures:

Test aes_stress_all_with_rand_reset has 2 failures.

3.aes_stress_all_with_rand_reset.103422965774367891200688664135832623898863352893875889913137009777130733982915
Line 944, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 352189787 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 352189787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aes_stress_all_with_rand_reset.103985607706487108175496116981743171091180059285489845638978791293905730400043
Line 1038, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 682882687 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 682882687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 62.aes_core_fi.82120408946185946234740550111122878283316558920438444922528862489238895661036
    Line 310, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/62.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10059771266 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x5f270884, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10059771266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```