AES/UNMASKED Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 wake_up aes_wake_up 0 1 0.00
V1 smoke aes_smoke 0 50 0.00
V1 csr_hw_reset aes_csr_hw_reset 3.000s 71.313us 5 5 100.00
V1 csr_rw aes_csr_rw 4.000s 119.059us 20 20 100.00
V1 csr_bit_bash aes_csr_bit_bash 11.000s 2.461ms 5 5 100.00
V1 csr_aliasing aes_csr_aliasing 5.000s 179.526us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aes_csr_mem_rw_with_rand_reset 4.000s 96.993us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aes_csr_rw 4.000s 119.059us 20 20 100.00
aes_csr_aliasing 5.000s 179.526us 5 5 100.00
V1 TOTAL 55 106 51.89
V2 algorithm aes_smoke 0 50 0.00
aes_config_error 0 50 0.00
aes_stress 0 50 0.00
V2 key_length aes_smoke 0 50 0.00
aes_config_error 0 50 0.00
aes_stress 0 50 0.00
V2 back2back aes_stress 0 50 0.00
aes_b2b 0 50 0.00
V2 backpressure aes_stress 0 50 0.00
V2 multi_message aes_smoke 0 50 0.00
aes_config_error 0 50 0.00
aes_stress 0 50 0.00
aes_alert_reset 0 50 0.00
V2 failure_test aes_man_cfg_err 0 50 0.00
aes_config_error 0 50 0.00
aes_alert_reset 0 50 0.00
V2 trigger_clear_test aes_clear 0 50 0.00
V2 nist_test_vectors aes_nist_vectors 0 1 0.00
V2 reset_recovery aes_alert_reset 0 50 0.00
V2 stress aes_stress 0 50 0.00
V2 sideload aes_stress 0 50 0.00
aes_sideload 0 50 0.00
V2 deinitialization aes_deinit 0 50 0.00
V2 stress_all aes_stress_all 0 10 0.00
V2 alert_test aes_alert_test 0 50 0.00
V2 tl_d_oob_addr_access aes_tl_errors 6.000s 157.663us 20 20 100.00
V2 tl_d_illegal_access aes_tl_errors 6.000s 157.663us 20 20 100.00
V2 tl_d_outstanding_access aes_csr_hw_reset 3.000s 71.313us 5 5 100.00
aes_csr_rw 4.000s 119.059us 20 20 100.00
aes_csr_aliasing 5.000s 179.526us 5 5 100.00
aes_same_csr_outstanding 4.000s 85.069us 20 20 100.00
V2 tl_d_partial_access aes_csr_hw_reset 3.000s 71.313us 5 5 100.00
aes_csr_rw 4.000s 119.059us 20 20 100.00
aes_csr_aliasing 5.000s 179.526us 5 5 100.00
aes_same_csr_outstanding 4.000s 85.069us 20 20 100.00
V2 TOTAL 40 501 7.98
V2S reseeding aes_reseed 0 50 0.00
V2S fault_inject aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_cipher_fi 0 350 0.00
V2S shadow_reg_update_error aes_shadow_reg_errors 4.000s 89.091us 20 20 100.00
V2S shadow_reg_read_clear_staged_value aes_shadow_reg_errors 4.000s 89.091us 20 20 100.00
V2S shadow_reg_storage_error aes_shadow_reg_errors 4.000s 89.091us 20 20 100.00
V2S shadowed_reset_glitch aes_shadow_reg_errors 4.000s 89.091us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw aes_shadow_reg_errors_with_csr_rw 4.000s 163.330us 20 20 100.00
V2S tl_intg_err aes_sec_cm 0 5 0.00
aes_tl_intg_err 6.000s 641.580us 20 20 100.00
V2S sec_cm_bus_integrity aes_tl_intg_err 6.000s 641.580us 20 20 100.00
V2S sec_cm_lc_escalate_en_intersig_mubi aes_alert_reset 0 50 0.00
V2S sec_cm_main_config_shadow aes_shadow_reg_errors 4.000s 89.091us 20 20 100.00
V2S sec_cm_main_config_sparse aes_smoke 0 50 0.00
aes_stress 0 50 0.00
aes_alert_reset 0 50 0.00
aes_core_fi 0 70 0.00
V2S sec_cm_aux_config_shadow aes_shadow_reg_errors 4.000s 89.091us 20 20 100.00
V2S sec_cm_aux_config_regwen aes_readability 0 50 0.00
aes_stress 0 50 0.00
V2S sec_cm_key_sideload aes_stress 0 50 0.00
aes_sideload 0 50 0.00
V2S sec_cm_key_sw_unreadable aes_readability 0 50 0.00
V2S sec_cm_data_reg_sw_unreadable aes_readability 0 50 0.00
V2S sec_cm_key_sec_wipe aes_readability 0 50 0.00
V2S sec_cm_iv_config_sec_wipe aes_readability 0 50 0.00
V2S sec_cm_data_reg_sec_wipe aes_readability 0 50 0.00
V2S sec_cm_data_reg_key_sca aes_stress 0 50 0.00
V2S sec_cm_key_masking aes_stress 0 50 0.00
V2S sec_cm_main_fsm_sparse aes_fi 0 50 0.00
V2S sec_cm_main_fsm_redun aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_cipher_fi 0 350 0.00
aes_ctr_fi 0 50 0.00
V2S sec_cm_cipher_fsm_sparse aes_fi 0 50 0.00
V2S sec_cm_cipher_fsm_redun aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_cipher_fi 0 350 0.00
V2S sec_cm_cipher_ctr_redun aes_cipher_fi 0 350 0.00
V2S sec_cm_ctr_fsm_sparse aes_fi 0 50 0.00
V2S sec_cm_ctr_fsm_redun aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_ctr_fi 0 50 0.00
V2S sec_cm_ctrl_sparse aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_cipher_fi 0 350 0.00
aes_ctr_fi 0 50 0.00
V2S sec_cm_main_fsm_global_esc aes_alert_reset 0 50 0.00
V2S sec_cm_main_fsm_local_esc aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_cipher_fi 0 350 0.00
aes_ctr_fi 0 50 0.00
V2S sec_cm_cipher_fsm_local_esc aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_cipher_fi 0 350 0.00
aes_ctr_fi 0 50 0.00
V2S sec_cm_ctr_fsm_local_esc aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_ctr_fi 0 50 0.00
V2S sec_cm_data_reg_local_esc aes_fi 0 50 0.00
aes_control_fi 0 300 0.00
aes_cipher_fi 0 350 0.00
V2S TOTAL 60 985 6.09
V3 stress_all_with_rand_reset aes_stress_all_with_rand_reset 0 10 0.00
V3 TOTAL 0 10 0.00
TOTAL 155 1602 9.68

Testplan Progress

Items Total Written Passing Progress
V1 7 7 5 71.43
V2 13 13 2 15.38
V2S 11 11 3 27.27
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
83.99 99.38 98.15 99.87 99.74 44.47 -- 98.03 43.64

Failure Buckets

Past Results