AES/UNMASKED Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	67.883us	1	1	100.00
V1	smoke	aes_smoke	8.000s	94.416us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	61.623us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	65.040us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	10.000s	623.857us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	5.000s	202.659us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	94.321us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	65.040us	20	20	100.00
		aes_csr_aliasing	5.000s	202.659us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	8.000s	94.416us	50	50	100.00
		aes_config_error	8.000s	326.195us	50	50	100.00
		aes_stress	8.000s	252.190us	50	50	100.00
V2	key_length	aes_smoke	8.000s	94.416us	50	50	100.00
		aes_config_error	8.000s	326.195us	50	50	100.00
		aes_stress	8.000s	252.190us	50	50	100.00
V2	back2back	aes_stress	8.000s	252.190us	50	50	100.00
		aes_b2b	17.000s	236.098us	50	50	100.00
V2	backpressure	aes_stress	8.000s	252.190us	50	50	100.00
V2	multi_message	aes_smoke	8.000s	94.416us	50	50	100.00
		aes_config_error	8.000s	326.195us	50	50	100.00
		aes_stress	8.000s	252.190us	50	50	100.00
		aes_alert_reset	13.000s	104.156us	50	50	100.00
V2	failure_test	aes_man_cfg_err	8.000s	65.185us	50	50	100.00
		aes_config_error	8.000s	326.195us	50	50	100.00
		aes_alert_reset	13.000s	104.156us	50	50	100.00
V2	trigger_clear_test	aes_clear	13.000s	230.440us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	182.286us	1	1	100.00
V2	reset_recovery	aes_alert_reset	13.000s	104.156us	50	50	100.00
V2	stress	aes_stress	8.000s	252.190us	50	50	100.00
V2	sideload	aes_stress	8.000s	252.190us	50	50	100.00
		aes_sideload	14.000s	176.905us	50	50	100.00
V2	deinitialization	aes_deinit	9.000s	83.980us	50	50	100.00
V2	stress_all	aes_stress_all	25.000s	5.329ms	10	10	100.00
V2	alert_test	aes_alert_test	8.000s	102.246us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	7.000s	955.292us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	7.000s	955.292us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	61.623us	5	5	100.00
		aes_csr_rw	4.000s	65.040us	20	20	100.00
		aes_csr_aliasing	5.000s	202.659us	5	5	100.00
		aes_same_csr_outstanding	4.000s	96.675us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	61.623us	5	5	100.00
		aes_csr_rw	4.000s	65.040us	20	20	100.00
		aes_csr_aliasing	5.000s	202.659us	5	5	100.00
		aes_same_csr_outstanding	4.000s	96.675us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	13.000s	69.892us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_cipher_fi	51.000s	31.533ms	325	350	92.86
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	67.044us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	67.044us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	67.044us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	67.044us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	421.192us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	1.248ms	5	5	100.00
		aes_tl_intg_err	7.000s	835.754us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	7.000s	835.754us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	13.000s	104.156us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	67.044us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	8.000s	94.416us	50	50	100.00
		aes_stress	8.000s	252.190us	50	50	100.00
		aes_alert_reset	13.000s	104.156us	50	50	100.00
		aes_core_fi	6.717m	10.013ms	62	70	88.57
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	67.044us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	12.000s	79.467us	50	50	100.00
		aes_stress	8.000s	252.190us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	8.000s	252.190us	50	50	100.00
		aes_sideload	14.000s	176.905us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	12.000s	79.467us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	12.000s	79.467us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	12.000s	79.467us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	12.000s	79.467us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	12.000s	79.467us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	8.000s	252.190us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	8.000s	252.190us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	57.278us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_cipher_fi	51.000s	31.533ms	325	350	92.86
		aes_ctr_fi	13.000s	96.531us	49	50	98.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	57.278us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_cipher_fi	51.000s	31.533ms	325	350	92.86
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	51.000s	31.533ms	325	350	92.86
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	57.278us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_ctr_fi	13.000s	96.531us	49	50	98.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_cipher_fi	51.000s	31.533ms	325	350	92.86
		aes_ctr_fi	13.000s	96.531us	49	50	98.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	13.000s	104.156us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_cipher_fi	51.000s	31.533ms	325	350	92.86
		aes_ctr_fi	13.000s	96.531us	49	50	98.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_cipher_fi	51.000s	31.533ms	325	350	92.86
		aes_ctr_fi	13.000s	96.531us	49	50	98.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_ctr_fi	13.000s	96.531us	49	50	98.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	57.278us	50	50	100.00
		aes_control_fi	51.000s	65.642ms	278	300	92.67
		aes_cipher_fi	51.000s	31.533ms	325	350	92.86
V2S		TOTAL			929	985	94.31
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	3.417m	17.348ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.13	97.46	94.26	98.77	93.57	97.72	91.11	98.66	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 30 failures:
- Test aes_control_fi has 14 failures.
  - 5.aes_control_fi.62737201267066665478642832613143688415414732389304036025941101214334891633346
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_control_fi/latest/run.log
```
  Job ID: smart:fd24854e-1071-43f6-a1d1-cfa488dccefa
```
  - 11.aes_control_fi.89460546602154309186492422812652998750541886078215007482801738258132497669702
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job ID: smart:1896d2bd-0db6-4736-a5de-97c572c588fd
```
  - ... and 12 more failures.
- Test aes_cipher_fi has 15 failures.
  - 10.aes_cipher_fi.6185378099208135537105355292228899389444562609469724583045330687949129655288
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job ID: smart:08db2675-6b03-4844-bf73-273d317c0432
```
  - 21.aes_cipher_fi.115438886260649065085311786052813998710839420408966482414498359763956247571620
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/21.aes_cipher_fi/latest/run.log
```
  Job ID: smart:5619b24c-b6c4-423f-aca7-8cd5066253a1
```
  - ... and 13 more failures.
- Test aes_ctr_fi has 1 failures.
  - 28.aes_ctr_fi.21697193442296894973576105704116218801887418834951795917663044476578985876877
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/28.aes_ctr_fi/latest/run.log
```
  Job ID: smart:ff333e1a-5e7e-4f63-a4eb-f82939b373d6
```
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 31.aes_cipher_fi.9412911923353114571313869498350870315598262283418450611486122568176002954929
    Line 319, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/31.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10004198236 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004198236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 76.aes_cipher_fi.87792875091201188492393150843590084387622556880804183387772671546877129663735
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/76.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006958316 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006958316 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 8 failures:
- Test aes_control_fi has 8 failures.
  - 20.aes_control_fi.101568221234257439898332790330412793804862662887897948977156999086728710871755
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/20.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003136628 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003136628 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 110.aes_control_fi.101458058947886977933507940143776987179034698609642743617233016105267704106123
    Line 327, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/110.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10016255261 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016255261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.53946566826283883871435414216171331069154652161921663133349123800078021639381
Line 744, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 175698323 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 175698323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.52022514596349086712301169567674312549123828188919402750615215488705906416534
Line 883, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6839639178 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6839639178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

2.aes_stress_all_with_rand_reset.24876001249310907231563678998888160685751663624193283117136677054869565919556
Line 806, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6187392917 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 6187392917 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.53009189636402764793184210253406975645952459690794713285677404713116621068665
Line 879, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2821434542 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2821434542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_core_fi has 4 failures.
  - 3.aes_core_fi.85635023087581441083911626397342571033663480246675971246483054289543659154149
    Line 313, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002312022 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002312022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_core_fi.99910125476766197440307751972292121530118909458155004636122252689682195779595
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008997890 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008997890 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 10.aes_core_fi.62182081547223976919798741760258134643326884558278511940066403952630663969078
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015726572 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015726572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_core_fi.535371095583060281001326666885085763677001186918934669047180415223369868911
    Line 317, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/52.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10061543292 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10061543292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 8.aes_core_fi.49360243245589452498184912576220400372678823248044343803841006875700136067331
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/8.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10040058380 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x93683684, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10040058380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 56.aes_core_fi.59056881697632456257828387834093778364585999967150990328596808097476354964614
    Line 324, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012713050 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x29e4d484, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
  UVM_INFO @ 10012713050 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```