AES/UNMASKED Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: XCELIUM

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	53.631us	1	1	100.00
V1	smoke	aes_smoke	4.000s	116.265us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	3.000s	55.771us	5	5	100.00
V1	csr_rw	aes_csr_rw	3.000s	151.389us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	320.702us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	4.000s	132.059us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	4.000s	76.749us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	3.000s	151.389us	20	20	100.00
		aes_csr_aliasing	4.000s	132.059us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	4.000s	116.265us	50	50	100.00
		aes_config_error	8.000s	226.543us	50	50	100.00
		aes_stress	6.000s	169.547us	50	50	100.00
V2	key_length	aes_smoke	4.000s	116.265us	50	50	100.00
		aes_config_error	8.000s	226.543us	50	50	100.00
		aes_stress	6.000s	169.547us	50	50	100.00
V2	back2back	aes_stress	6.000s	169.547us	50	50	100.00
		aes_b2b	11.000s	1.726ms	50	50	100.00
V2	backpressure	aes_stress	6.000s	169.547us	50	50	100.00
V2	multi_message	aes_smoke	4.000s	116.265us	50	50	100.00
		aes_config_error	8.000s	226.543us	50	50	100.00
		aes_stress	6.000s	169.547us	50	50	100.00
		aes_alert_reset	6.000s	249.267us	50	50	100.00
V2	failure_test	aes_man_cfg_err	4.000s	119.606us	50	50	100.00
		aes_config_error	8.000s	226.543us	50	50	100.00
		aes_alert_reset	6.000s	249.267us	50	50	100.00
V2	trigger_clear_test	aes_clear	6.000s	201.042us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	6.000s	371.541us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	249.267us	50	50	100.00
V2	stress	aes_stress	6.000s	169.547us	50	50	100.00
V2	sideload	aes_stress	6.000s	169.547us	50	50	100.00
		aes_sideload	6.000s	385.929us	50	50	100.00
V2	deinitialization	aes_deinit	7.000s	206.881us	50	50	100.00
V2	stress_all	aes_stress_all	30.000s	1.013ms	10	10	100.00
V2	alert_test	aes_alert_test	3.000s	53.648us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	14.000s	142.500us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	14.000s	142.500us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	3.000s	55.771us	5	5	100.00
		aes_csr_rw	3.000s	151.389us	20	20	100.00
		aes_csr_aliasing	4.000s	132.059us	5	5	100.00
		aes_same_csr_outstanding	8.000s	79.769us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	3.000s	55.771us	5	5	100.00
		aes_csr_rw	3.000s	151.389us	20	20	100.00
		aes_csr_aliasing	4.000s	132.059us	5	5	100.00
		aes_same_csr_outstanding	8.000s	79.769us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	13.000s	925.445us	50	50	100.00
V2S	fault_inject	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_cipher_fi	47.000s	10.002ms	326	350	93.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	7.000s	87.882us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	7.000s	87.882us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	7.000s	87.882us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	7.000s	87.882us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	4.000s	106.283us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	898.869us	5	5	100.00
		aes_tl_intg_err	9.000s	278.214us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	9.000s	278.214us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	249.267us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	7.000s	87.882us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	4.000s	116.265us	50	50	100.00
		aes_stress	6.000s	169.547us	50	50	100.00
		aes_alert_reset	6.000s	249.267us	50	50	100.00
		aes_core_fi	4.383m	10.018ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	7.000s	87.882us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	4.000s	70.668us	50	50	100.00
		aes_stress	6.000s	169.547us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	169.547us	50	50	100.00
		aes_sideload	6.000s	385.929us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	4.000s	70.668us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	4.000s	70.668us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	4.000s	70.668us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	4.000s	70.668us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	4.000s	70.668us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	169.547us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	169.547us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	4.000s	96.918us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_cipher_fi	47.000s	10.002ms	326	350	93.14
		aes_ctr_fi	4.000s	219.365us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	4.000s	96.918us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_cipher_fi	47.000s	10.002ms	326	350	93.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	47.000s	10.002ms	326	350	93.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	4.000s	96.918us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_ctr_fi	4.000s	219.365us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_cipher_fi	47.000s	10.002ms	326	350	93.14
		aes_ctr_fi	4.000s	219.365us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	249.267us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_cipher_fi	47.000s	10.002ms	326	350	93.14
		aes_ctr_fi	4.000s	219.365us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_cipher_fi	47.000s	10.002ms	326	350	93.14
		aes_ctr_fi	4.000s	219.365us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_ctr_fi	4.000s	219.365us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	4.000s	96.918us	50	50	100.00
		aes_control_fi	49.000s	32.840ms	269	300	89.67
		aes_cipher_fi	47.000s	10.002ms	326	350	93.14
V2S		TOTAL			927	985	94.11
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	19.850m	43.750ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1534	1602	95.76

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.46	94.26	98.81	93.68	97.72	93.33	98.85	95.61

Failure Buckets

Job aes_unmasked-sim-xcelium_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 33 failures:
- Test aes_cipher_fi has 12 failures.
  - 3.aes_cipher_fi.104284565956821627705069908122991599410094163846936976736361677366798532869995
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job ID: smart:8b368245-7322-4e22-a716-ba5ffaad03cd
```
  - 4.aes_cipher_fi.59757201162859724575176207629838777056193858735176831610993581373953467385196
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_cipher_fi/latest/run.log
```
  Job ID: smart:0901c188-367f-4ed9-b1e7-ecf27a4c30e0
```
  - ... and 10 more failures.
- Test aes_control_fi has 21 failures.
  - 4.aes_control_fi.23632926626486975737037871539700402211626786226188076071907487817502955403511
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job ID: smart:ae536756-9978-4967-aea6-e36baf62887e
```
  - 12.aes_control_fi.58750576200936405025124780253546965845263398104990956104513738698152780248313
    Log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  Job ID: smart:c0de5e2f-14b3-4e4e-838e-fe1739e07b6c
```
  - ... and 19 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 24.aes_cipher_fi.93246329877572175686716723309392446305710721969334264411079190009495486270812
    Line 315, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10020304522 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020304522 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 32.aes_cipher_fi.109898849708499922674269560335087739954814659376659210036591676529238692365750
    Line 329, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/32.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003210294 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003210294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_control_fi has 10 failures.
  - 10.aes_control_fi.46342847791954049128154514090173890379633526069553681757772290490766983819833
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10020770932 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10020770932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 34.aes_control_fi.42776746197245166494507579064986464143916873284537255330119287913344992042084
    Line 321, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10022896399 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022896399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

Exit reason: Error: User command failed UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.85521692927423104712994684440520952326560393933700794398396480473613082324779
Line 1479, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 419132629 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 419132629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.2901533565343900207739675186232704030677028457415667460323926531255977476844
Line 1210, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 721086086 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 721086086 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

1.aes_stress_all_with_rand_reset.46601462498689864102709604961832264744691434222545346731442625865358665465450
Line 1422, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 43749741399 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 43749741399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.53922762527835535796866876174584414869171868718163720446403496349176710757439
Line 1053, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 952130158 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 952130158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 5.aes_core_fi.58769038082501928248136946497459818306726390367386624605735196633536903312023
    Line 316, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/5.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013067573 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013067573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:549) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.47089296804227887613119917145392139196921437657753409697456582573691681686414
    Line 551, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 640061504 ps: (cip_base_vseq.sv:549) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 640061504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Exit reason: Error: User command failed UVM_ERROR (cip_base_vseq.sv:837) [aes_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.71993699563741990290346773159387960451677620148484356062521764542184157823894
    Line 418, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 9079388221 ps: (cip_base_vseq.sv:837) [uvm_test_top.env.virtual_sequencer.aes_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 9079388221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 34.aes_core_fi.47554690463437708061753646794304288321756873957294618134229140410382155293224
    Line 314, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/34.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10062517388 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10062517388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=14) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 44.aes_core_fi.8756128124896082572322835463096566115546183109678761454544039644857465416372
    Line 320, in log /container/opentitan-public/scratch/os_regression/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018144964 ps: (csr_utils_pkg.sv:597) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x41ec1584, Comparison=CompareOpEq, exp_data=0x0, call_count=14)
  UVM_INFO @ 10018144964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```