AES/UNMASKED Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: XCELIUM

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	15.000s	88.236us	1	1	100.00
V1	smoke	aes_smoke	56.000s	67.364us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	83.210us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	53.887us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	12.000s	1.495ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	293.130us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	109.778us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	53.887us	20	20	100.00
		aes_csr_aliasing	6.000s	293.130us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	56.000s	67.364us	50	50	100.00
		aes_config_error	1.183m	325.683us	50	50	100.00
		aes_stress	1.267m	57.827us	50	50	100.00
V2	key_length	aes_smoke	56.000s	67.364us	50	50	100.00
		aes_config_error	1.183m	325.683us	50	50	100.00
		aes_stress	1.267m	57.827us	50	50	100.00
V2	back2back	aes_stress	1.267m	57.827us	50	50	100.00
		aes_b2b	1.717m	104.610us	50	50	100.00
V2	backpressure	aes_stress	1.267m	57.827us	50	50	100.00
V2	multi_message	aes_smoke	56.000s	67.364us	50	50	100.00
		aes_config_error	1.183m	325.683us	50	50	100.00
		aes_stress	1.267m	57.827us	50	50	100.00
		aes_alert_reset	1.150m	67.700us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.217m	71.857us	50	50	100.00
		aes_config_error	1.183m	325.683us	50	50	100.00
		aes_alert_reset	1.150m	67.700us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.700m	181.090us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	17.000s	376.242us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.150m	67.700us	50	50	100.00
V2	stress	aes_stress	1.267m	57.827us	50	50	100.00
V2	sideload	aes_stress	1.267m	57.827us	50	50	100.00
		aes_sideload	58.000s	78.947us	50	50	100.00
V2	deinitialization	aes_deinit	59.000s	161.015us	50	50	100.00
V2	stress_all	aes_stress_all	32.000s	528.418us	9	10	90.00
V2	alert_test	aes_alert_test	1.200m	79.156us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	130.929us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	130.929us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	83.210us	5	5	100.00
		aes_csr_rw	4.000s	53.887us	20	20	100.00
		aes_csr_aliasing	6.000s	293.130us	5	5	100.00
		aes_same_csr_outstanding	5.000s	93.121us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	83.210us	5	5	100.00
		aes_csr_rw	4.000s	53.887us	20	20	100.00
		aes_csr_aliasing	6.000s	293.130us	5	5	100.00
		aes_same_csr_outstanding	5.000s	93.121us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.100m	100.138us	50	50	100.00
V2S	fault_inject	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_cipher_fi	59.000s	68.782us	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	4.000s	62.399us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	4.000s	62.399us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	4.000s	62.399us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	4.000s	62.399us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	5.000s	75.708us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	14.000s	657.624us	5	5	100.00
		aes_tl_intg_err	6.000s	701.364us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	6.000s	701.364us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.150m	67.700us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	4.000s	62.399us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	56.000s	67.364us	50	50	100.00
		aes_stress	1.267m	57.827us	50	50	100.00
		aes_alert_reset	1.150m	67.700us	50	50	100.00
		aes_core_fi	5.500m	10.011ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	4.000s	62.399us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.017m	66.388us	50	50	100.00
		aes_stress	1.267m	57.827us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.267m	57.827us	50	50	100.00
		aes_sideload	58.000s	78.947us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.017m	66.388us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.017m	66.388us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.017m	66.388us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.017m	66.388us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.017m	66.388us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.267m	57.827us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.267m	57.827us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.367m	71.479us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_cipher_fi	59.000s	68.782us	320	350	91.43
		aes_ctr_fi	49.000s	61.678us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.367m	71.479us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_cipher_fi	59.000s	68.782us	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	68.782us	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.367m	71.479us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_ctr_fi	49.000s	61.678us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_cipher_fi	59.000s	68.782us	320	350	91.43
		aes_ctr_fi	49.000s	61.678us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.150m	67.700us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_cipher_fi	59.000s	68.782us	320	350	91.43
		aes_ctr_fi	49.000s	61.678us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_cipher_fi	59.000s	68.782us	320	350	91.43
		aes_ctr_fi	49.000s	61.678us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_ctr_fi	49.000s	61.678us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.367m	71.479us	50	50	100.00
		aes_control_fi	59.000s	55.229us	275	300	91.67
		aes_cipher_fi	59.000s	68.782us	320	350	91.43
V2S		TOTAL			925	985	93.91
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	33.000s	1.980ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1531	1602	95.57

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	8	72.73
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.17	97.50	94.35	98.75	93.71	97.72	91.11	98.85	96.01

Failure Buckets

Job timed out after * minutes has 32 failures:
- Test aes_cipher_fi has 18 failures.
  - 3.aes_cipher_fi.68136207615907278640429360662335572489659260307807476918895737702496762281907
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 6.aes_cipher_fi.111086593380347411069039386998140593254856432974010951270661414548165088926754
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 16 more failures.
- Test aes_control_fi has 14 failures.
  - 44.aes_control_fi.45346226195986553785295578053045492111881211046413073136703911475941515010498
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/44.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 66.aes_control_fi.99829523474566565934285530205470153376037325389892121645747219062399915399692
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/66.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 12 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 12 failures:
- Test aes_cipher_fi has 12 failures.
  - 30.aes_cipher_fi.9448802575265758965577963002177411750024728770784448786085770283304454517892
    Line 132, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/30.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005624624 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005624624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 52.aes_cipher_fi.43297743726678050025955458070932877409877943570973855053800033641071036582463
    Line 144, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/52.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006825678 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006825678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 10 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 22.aes_control_fi.75404550732275573191344672629126719436915288316307307121242370963787975179023
    Line 132, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/22.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003383019 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003383019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 25.aes_control_fi.49840822779615845382434381567729418601805047367398209072068041008818248349113
    Line 130, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/25.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10008408085 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008408085 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.99941474072677953572290574321735922772995699771801918697562322707242414202900
Line 786, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 981304987 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 981304987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.85156321813848607457635914698855635917897312797171310708417158227198159008682
Line 527, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 594641278 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 594641278 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 2 failures:
- Test aes_core_fi has 2 failures.
  - 22.aes_core_fi.68946617311766449474424274320974373474351492697874612723511643990450864739182
    Line 128, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10017438267 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x3439b484, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10017438267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_core_fi.72538952945691914208868060031601440169735332319160387757781219074205165649118
    Line 134, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10011108901 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x7b14f684, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10011108901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=11) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 0.aes_core_fi.83317037129991651172511009481844597307849267426002479908170381459071396537450
    Line 135, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/0.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10019423408 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xef3eb584, Comparison=CompareOpEq, exp_data=0x0, call_count=11)
  UVM_INFO @ 10019423408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.79208824561104658224292412437393760045258867340057370587630894352644127500167
    Line 156, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 213713675 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 213713675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/earlgrey_*_*_*_*_*_*_RC0/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_stress_all has 1 failures.

4.aes_stress_all.111760785247961049940522079413817968968388075691578793376044866857802390126017
Line 43421, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/4.aes_stress_all/latest/run.log

  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 219765746 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 219753088 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 219765746 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 219753088 PS)
  UVM_ERROR @ 219765746 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut

UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 9.aes_stress_all_with_rand_reset.76879841529051449660020262592712877958475398137499131563361370684361653817417
    Line 154, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  17171136 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  17171136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 43.aes_core_fi.63991357233908983665661844829011487930730003645807100236539488327878934648852
    Line 133, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/43.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022499302 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x29442f84, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10022499302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 56.aes_core_fi.10247433189655884630655135571032873082064323185939060748344442434070800576368
    Line 128, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aes_unmasked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002516254 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002516254 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```