AES/UNMASKED Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: XCELIUM

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	53.761us	1	1	100.00
V1	smoke	aes_smoke	54.000s	89.246us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	7.000s	93.264us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.017m	50.514us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	11.000s	836.421us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	8.000s	222.911us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	53.000s	91.983us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.017m	50.514us	20	20	100.00
		aes_csr_aliasing	8.000s	222.911us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	54.000s	89.246us	50	50	100.00
		aes_config_error	54.000s	85.018us	50	50	100.00
		aes_stress	53.000s	59.333us	50	50	100.00
V2	key_length	aes_smoke	54.000s	89.246us	50	50	100.00
		aes_config_error	54.000s	85.018us	50	50	100.00
		aes_stress	53.000s	59.333us	50	50	100.00
V2	back2back	aes_stress	53.000s	59.333us	50	50	100.00
		aes_b2b	54.000s	92.449us	50	50	100.00
V2	backpressure	aes_stress	53.000s	59.333us	50	50	100.00
V2	multi_message	aes_smoke	54.000s	89.246us	50	50	100.00
		aes_config_error	54.000s	85.018us	50	50	100.00
		aes_stress	53.000s	59.333us	50	50	100.00
		aes_alert_reset	33.000s	167.072us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.150m	53.852us	50	50	100.00
		aes_config_error	54.000s	85.018us	50	50	100.00
		aes_alert_reset	33.000s	167.072us	50	50	100.00
V2	trigger_clear_test	aes_clear	58.000s	100.658us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	708.007us	1	1	100.00
V2	reset_recovery	aes_alert_reset	33.000s	167.072us	50	50	100.00
V2	stress	aes_stress	53.000s	59.333us	50	50	100.00
V2	sideload	aes_stress	53.000s	59.333us	50	50	100.00
		aes_sideload	37.000s	59.959us	50	50	100.00
V2	deinitialization	aes_deinit	36.000s	75.202us	50	50	100.00
V2	stress_all	aes_stress_all	24.000s	658.275us	10	10	100.00
V2	alert_test	aes_alert_test	35.000s	94.351us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	48.000s	169.670us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	48.000s	169.670us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	7.000s	93.264us	5	5	100.00
		aes_csr_rw	1.017m	50.514us	20	20	100.00
		aes_csr_aliasing	8.000s	222.911us	5	5	100.00
		aes_same_csr_outstanding	50.000s	107.069us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	7.000s	93.264us	5	5	100.00
		aes_csr_rw	1.017m	50.514us	20	20	100.00
		aes_csr_aliasing	8.000s	222.911us	5	5	100.00
		aes_same_csr_outstanding	50.000s	107.069us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	38.000s	62.859us	50	50	100.00
V2S	fault_inject	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_cipher_fi	58.000s	15.781ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	34.000s	52.771us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	34.000s	52.771us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	34.000s	52.771us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	34.000s	52.771us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	39.000s	100.656us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	6.000s	582.274us	5	5	100.00
		aes_tl_intg_err	32.000s	205.499us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	32.000s	205.499us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	33.000s	167.072us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	34.000s	52.771us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	54.000s	89.246us	50	50	100.00
		aes_stress	53.000s	59.333us	50	50	100.00
		aes_alert_reset	33.000s	167.072us	50	50	100.00
		aes_core_fi	5.733m	10.007ms	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	34.000s	52.771us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	57.000s	62.178us	50	50	100.00
		aes_stress	53.000s	59.333us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	53.000s	59.333us	50	50	100.00
		aes_sideload	37.000s	59.959us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	57.000s	62.178us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	57.000s	62.178us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	57.000s	62.178us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	57.000s	62.178us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	57.000s	62.178us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	53.000s	59.333us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	53.000s	59.333us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	40.000s	96.666us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_cipher_fi	58.000s	15.781ms	320	350	91.43
		aes_ctr_fi	37.000s	52.506us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	40.000s	96.666us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_cipher_fi	58.000s	15.781ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	58.000s	15.781ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	40.000s	96.666us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_ctr_fi	37.000s	52.506us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_cipher_fi	58.000s	15.781ms	320	350	91.43
		aes_ctr_fi	37.000s	52.506us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	33.000s	167.072us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_cipher_fi	58.000s	15.781ms	320	350	91.43
		aes_ctr_fi	37.000s	52.506us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_cipher_fi	58.000s	15.781ms	320	350	91.43
		aes_ctr_fi	37.000s	52.506us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_ctr_fi	37.000s	52.506us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	40.000s	96.666us	49	50	98.00
		aes_control_fi	57.000s	10.004ms	279	300	93.00
		aes_cipher_fi	58.000s	15.781ms	320	350	91.43
V2S		TOTAL			929	985	94.31
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	21.000s	2.233ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1536	1602	95.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.14	97.43	94.18	98.77	93.63	97.64	91.11	98.85	96.41

Failure Buckets

Job timed out after * minutes has 28 failures:
- Test aes_control_fi has 13 failures.
  - 11.aes_control_fi.94255745547301435242390417820943635156089392999292738807005860175275234043175
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/11.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 13.aes_control_fi.24287773873283867994154023082653549369387149540366622752034327309124347601321
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/13.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
- Test aes_cipher_fi has 15 failures.
  - 40.aes_cipher_fi.72189515564707139781989968726607598296635338066409095204474878801118973381112
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/40.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 60.aes_cipher_fi.15863398497601618897115734512208007636280434563344998059703072429180684546285
    Log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/60.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 13 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 15 failures:
- Test aes_cipher_fi has 15 failures.
  - 47.aes_cipher_fi.14258289789871170716776678489406859140793448399981694011719317435028498457392
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/47.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10009332442 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009332442 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 103.aes_cipher_fi.81103328777051428956727555605515710530761470134452496868201142991348540140904
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/103.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007438960 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007438960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 13 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.43594335884338869920855314321016986981191051185592758568389653605364612470144
Line 602, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2232604759 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2232604759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aes_stress_all_with_rand_reset.77310889119908553973000047859364777348036921467619524870191213855744270916290
Line 285, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 738414279 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 738414279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 39.aes_control_fi.90667130047642167961604005862497892336000212681976458388988833297286077509205
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/39.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017445596 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017445596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 76.aes_control_fi.32076770303805171145307502442155828958545719624548106594652009162163530785416
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/76.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004231930 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004231930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 20.aes_core_fi.113670700531208875878747481676399891179433591809005814961116761223714224808949
    Line 140, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10010032749 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010032749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 56.aes_core_fi.37915626753717211037986127590762355814765279104104110895525263870499882468210
    Line 139, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/56.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015575945 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015575945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.70546593526051067921986064221869918664505258933294216920403046669375165905215
    Line 173, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  22370511 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  22370511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.aes_stress_all_with_rand_reset.22876568037620259530131342688543850880279530592546422156438715398097957739996
    Line 149, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  48334311 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  48334311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

20.aes_fi.49456978891059190292448742875749071503970930879397932191209198685633707981476
Line 2095, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/20.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 25040414 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 25000414 PS)
  UVM_ERROR @  25040414 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @  25040414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 23.aes_core_fi.3410766068844828214551629261175916394283058917497722579328761613070878021686
    Line 125, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/23.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007060609 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xaef14384, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10007060609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 162.aes_control_fi.91324285394189321327698855401061816370921339593402678064463279773438632412361
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_08_22/aes_unmasked-sim-xcelium/162.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```