AES/UNMASKED Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Simulator: XCELIUM

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	57.695us	1	1	100.00
V1	smoke	aes_smoke	2.667m	136.291us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	59.000s	103.097us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.600m	65.341us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.333m	858.024us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	1.583m	278.242us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.617m	58.091us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.600m	65.341us	20	20	100.00
		aes_csr_aliasing	1.583m	278.242us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	2.667m	136.291us	50	50	100.00
		aes_config_error	1.150m	161.210us	50	50	100.00
		aes_stress	1.500m	65.852us	50	50	100.00
V2	key_length	aes_smoke	2.667m	136.291us	50	50	100.00
		aes_config_error	1.150m	161.210us	50	50	100.00
		aes_stress	1.500m	65.852us	50	50	100.00
V2	back2back	aes_stress	1.500m	65.852us	50	50	100.00
		aes_b2b	2.100m	253.120us	50	50	100.00
V2	backpressure	aes_stress	1.500m	65.852us	50	50	100.00
V2	multi_message	aes_smoke	2.667m	136.291us	50	50	100.00
		aes_config_error	1.150m	161.210us	50	50	100.00
		aes_stress	1.500m	65.852us	50	50	100.00
		aes_alert_reset	2.017m	63.034us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.917m	112.263us	50	50	100.00
		aes_config_error	1.150m	161.210us	50	50	100.00
		aes_alert_reset	2.017m	63.034us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.050m	270.868us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	201.855us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.017m	63.034us	50	50	100.00
V2	stress	aes_stress	1.500m	65.852us	50	50	100.00
V2	sideload	aes_stress	1.500m	65.852us	50	50	100.00
		aes_sideload	1.383m	69.664us	50	50	100.00
V2	deinitialization	aes_deinit	1.183m	150.663us	50	50	100.00
V2	stress_all	aes_stress_all	1.033m	111.290us	9	10	90.00
V2	alert_test	aes_alert_test	1.367m	65.180us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.600m	192.963us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.600m	192.963us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	59.000s	103.097us	5	5	100.00
		aes_csr_rw	1.600m	65.341us	20	20	100.00
		aes_csr_aliasing	1.583m	278.242us	5	5	100.00
		aes_same_csr_outstanding	1.483m	67.949us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	59.000s	103.097us	5	5	100.00
		aes_csr_rw	1.600m	65.341us	20	20	100.00
		aes_csr_aliasing	1.583m	278.242us	5	5	100.00
		aes_same_csr_outstanding	1.483m	67.949us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	2.017m	54.230us	50	50	100.00
V2S	fault_inject	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_cipher_fi	1.017m	92.575us	288	350	82.29
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.583m	101.512us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.583m	101.512us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.583m	101.512us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.583m	101.512us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.567m	206.722us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	15.000s	442.151us	5	5	100.00
		aes_tl_intg_err	1.583m	923.086us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.583m	923.086us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.017m	63.034us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.583m	101.512us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	2.667m	136.291us	50	50	100.00
		aes_stress	1.500m	65.852us	50	50	100.00
		aes_alert_reset	2.017m	63.034us	50	50	100.00
		aes_core_fi	1.917m	132.907us	68	70	97.14
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.583m	101.512us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.417m	55.665us	50	50	100.00
		aes_stress	1.500m	65.852us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.500m	65.852us	50	50	100.00
		aes_sideload	1.383m	69.664us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.417m	55.665us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.417m	55.665us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.417m	55.665us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.417m	55.665us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.417m	55.665us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.500m	65.852us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.500m	65.852us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.033m	280.560us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_cipher_fi	1.017m	92.575us	288	350	82.29
		aes_ctr_fi	1.017m	85.663us	43	50	86.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.033m	280.560us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_cipher_fi	1.017m	92.575us	288	350	82.29
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	92.575us	288	350	82.29
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.033m	280.560us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_ctr_fi	1.017m	85.663us	43	50	86.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_cipher_fi	1.017m	92.575us	288	350	82.29
		aes_ctr_fi	1.017m	85.663us	43	50	86.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.017m	63.034us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_cipher_fi	1.017m	92.575us	288	350	82.29
		aes_ctr_fi	1.017m	85.663us	43	50	86.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_cipher_fi	1.017m	92.575us	288	350	82.29
		aes_ctr_fi	1.017m	85.663us	43	50	86.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_ctr_fi	1.017m	85.663us	43	50	86.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.033m	280.560us	49	50	98.00
		aes_control_fi	1.000m	52.101us	249	300	83.00
		aes_cipher_fi	1.017m	92.575us	288	350	82.29
V2S		TOTAL			862	985	87.51
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.233m	1.248ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1468	1602	91.64

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.15	97.46	94.26	98.77	93.60	97.64	93.33	98.85	96.01

Failure Buckets

Job timed out after * minutes has 105 failures:
- Test aes_control_fi has 46 failures.
  - 3.aes_control_fi.72170534710351852261724169856542194433481621096904704173255951229585727859289
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/3.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 7.aes_control_fi.81097738352714097547560726051141452522790988713308784608581994301193652139199
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 44 more failures.
- Test aes_ctr_fi has 7 failures.
  - 3.aes_ctr_fi.43214724945338650914780864245429294118301112709357982942982826928063697880333
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/3.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 8.aes_ctr_fi.30356436274831210452025971365387049955931083082047774716704212405848651898537
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/8.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 52 failures.
  - 6.aes_cipher_fi.39762423193527610082289094425656658541903595411125036825698918663016983902928
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_cipher_fi.22816917813223883836572830261624851394404032226441895944705576749318364500501
    Log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 50 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 10 failures:
- Test aes_cipher_fi has 10 failures.
  - 18.aes_cipher_fi.78435737331105108751239468224058849246158429305925263371824511312038434805990
    Line 141, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/18.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008954061 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008954061 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.aes_cipher_fi.54407132855963270622446385263100610547159795048125679991624619419177632002348
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/33.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10008757776 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008757776 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 8 failures:

Test aes_stress_all_with_rand_reset has 8 failures.

0.aes_stress_all_with_rand_reset.87625730219114791322723502398562969108834430223862548825479602392611367202029
Line 851, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 475758236 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 475758236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.108896352826868361068018922427863835470398587973486593180016137734274013886905
Line 1080, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 698038687 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 698038687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 43.aes_control_fi.77143678789159178132142810553432181840892697937494239474746228689145177329413
    Line 139, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10061151981 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10061151981 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 57.aes_control_fi.9409260775129171613354408097147205263642154689878145922763909240966520704548
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/57.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10017924594 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017924594 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 4.aes_stress_all_with_rand_reset.65851175614416806411651762474032916189205440022232769255984940255527925318729
    Line 193, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1575259825 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1575259825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.14422267044525782136657856114918780041425711648128519464769989147839390130376
    Line 558, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1260643493 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1260643493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:557) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all has 1 failures.
  - 6.aes_stress_all.9219631407446535718622120474304961346636956577012823618291005510952754728846
    Line 10126, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/6.aes_stress_all/latest/run.log
```
  UVM_ERROR @ 197738957 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 197738957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 9.aes_core_fi.59343229707309823023779953319821281466829221501291799733661884521379905846706
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/9.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012085894 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012085894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 28.aes_core_fi.51775655853444970120085101251929902702241733204955548220319609568717157663041
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10035552526 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10035552526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

42.aes_fi.48740977196527615837168593387096586143539270507300099089966561914960879224430
Line 451, in log /workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/42.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_28/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 1994294 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 1984294 PS)
  UVM_ERROR @   1994294 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @   1994294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---