AES/UNMASKED Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: XCELIUM

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	88.005us	1	1	100.00
V1	smoke	aes_smoke	1.750m	74.835us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	34.000s	69.370us	5	5	100.00
V1	csr_rw	aes_csr_rw	52.000s	67.182us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.067m	413.024us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	52.000s	298.452us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	55.000s	57.091us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	52.000s	67.182us	20	20	100.00
		aes_csr_aliasing	52.000s	298.452us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.750m	74.835us	50	50	100.00
		aes_config_error	1.767m	63.265us	50	50	100.00
		aes_stress	1.817m	96.202us	50	50	100.00
V2	key_length	aes_smoke	1.750m	74.835us	50	50	100.00
		aes_config_error	1.767m	63.265us	50	50	100.00
		aes_stress	1.817m	96.202us	50	50	100.00
V2	back2back	aes_stress	1.817m	96.202us	50	50	100.00
		aes_b2b	1.800m	141.515us	50	50	100.00
V2	backpressure	aes_stress	1.817m	96.202us	50	50	100.00
V2	multi_message	aes_smoke	1.750m	74.835us	50	50	100.00
		aes_config_error	1.767m	63.265us	50	50	100.00
		aes_stress	1.817m	96.202us	50	50	100.00
		aes_alert_reset	1.733m	100.330us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.783m	60.031us	50	50	100.00
		aes_config_error	1.767m	63.265us	50	50	100.00
		aes_alert_reset	1.733m	100.330us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.767m	122.141us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	10.000s	331.668us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.733m	100.330us	50	50	100.00
V2	stress	aes_stress	1.817m	96.202us	50	50	100.00
V2	sideload	aes_stress	1.817m	96.202us	50	50	100.00
		aes_sideload	1.750m	65.475us	50	50	100.00
V2	deinitialization	aes_deinit	1.767m	67.937us	50	50	100.00
V2	stress_all	aes_stress_all	41.000s	16.142ms	10	10	100.00
V2	alert_test	aes_alert_test	1.783m	161.141us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.117m	528.857us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.117m	528.857us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	34.000s	69.370us	5	5	100.00
		aes_csr_rw	52.000s	67.182us	20	20	100.00
		aes_csr_aliasing	52.000s	298.452us	5	5	100.00
		aes_same_csr_outstanding	1.000m	447.188us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	34.000s	69.370us	5	5	100.00
		aes_csr_rw	52.000s	67.182us	20	20	100.00
		aes_csr_aliasing	52.000s	298.452us	5	5	100.00
		aes_same_csr_outstanding	1.000m	447.188us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.783m	333.563us	50	50	100.00
V2S	fault_inject	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_cipher_fi	1.733m	55.265us	228	350	65.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.100m	77.931us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.100m	77.931us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.100m	77.931us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.100m	77.931us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.017m	519.451us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	7.000s	1.336ms	5	5	100.00
		aes_tl_intg_err	1.150m	218.737us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.150m	218.737us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.733m	100.330us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.100m	77.931us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.750m	74.835us	50	50	100.00
		aes_stress	1.817m	96.202us	50	50	100.00
		aes_alert_reset	1.733m	100.330us	50	50	100.00
		aes_core_fi	1.800m	138.966us	66	70	94.29
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.100m	77.931us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.733m	61.740us	49	50	98.00
		aes_stress	1.817m	96.202us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.817m	96.202us	50	50	100.00
		aes_sideload	1.750m	65.475us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.733m	61.740us	49	50	98.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.733m	61.740us	49	50	98.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.733m	61.740us	49	50	98.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.733m	61.740us	49	50	98.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.733m	61.740us	49	50	98.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.817m	96.202us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.817m	96.202us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.767m	139.957us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_cipher_fi	1.733m	55.265us	228	350	65.14
		aes_ctr_fi	1.750m	46.971us	40	50	80.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.767m	139.957us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_cipher_fi	1.733m	55.265us	228	350	65.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.733m	55.265us	228	350	65.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.767m	139.957us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_ctr_fi	1.750m	46.971us	40	50	80.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_cipher_fi	1.733m	55.265us	228	350	65.14
		aes_ctr_fi	1.750m	46.971us	40	50	80.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.733m	100.330us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_cipher_fi	1.733m	55.265us	228	350	65.14
		aes_ctr_fi	1.750m	46.971us	40	50	80.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_cipher_fi	1.733m	55.265us	228	350	65.14
		aes_ctr_fi	1.750m	46.971us	40	50	80.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_ctr_fi	1.750m	46.971us	40	50	80.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.767m	139.957us	50	50	100.00
		aes_control_fi	2.433m	10.002ms	223	300	74.33
		aes_cipher_fi	1.733m	55.265us	228	350	65.14
V2S		TOTAL			771	985	78.27
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	23.000s	1.187ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1378	1602	86.02

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.18	97.50	94.35	98.81	93.63	97.64	93.33	98.85	95.61

Failure Buckets

Job timed out after * minutes has 200 failures:
- Test aes_cipher_fi has 119 failures.
  - 3.aes_cipher_fi.43900181144595231947336116219073319892496050976882721143149396508171625576026
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 28.aes_cipher_fi.97478386798296290190818682655979119559400540471445128119229437456169423329362
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/28.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 117 more failures.
- Test aes_control_fi has 71 failures.
  - 28.aes_control_fi.25995405944994302417486361474427523330459139016531683542833409670817262384651
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/28.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 29.aes_control_fi.70031523892518384534304354632343699166195085515122606464404660613471507365149
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/29.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 69 more failures.
- Test aes_ctr_fi has 10 failures.
  - 28.aes_ctr_fi.110528294434664247428875664019517538560742472756318403790158277998141204452798
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/28.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 29.aes_ctr_fi.16310762279990126675729504886886374345227846456968889752793389505680929412995
    Log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/29.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 8 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.81006068551937699803354340706706360091246548598145527324755165487210160027995
Line 747, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 907672157 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 907672157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.38237129768714299880613245565240411271221005689469052801819375518337808494345
Line 168, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  18457500 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  18457500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 12.aes_control_fi.6421245858861146529401654218866033709631638676556152938353986150523784184080
    Line 132, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/12.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10002189756 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002189756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 77.aes_control_fi.78148737365898805222147078000407081095476772168408894293964048662755732346027
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/77.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006384472 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006384472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 3 failures:
- Test aes_stress_all_with_rand_reset has 3 failures.
  - 4.aes_stress_all_with_rand_reset.87350185406903041652469042537006060620930809931959579060289909872197638016692
    Line 148, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 173642350 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 173642350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.aes_stress_all_with_rand_reset.26001353936291047346411274984097168546455333534124200260424263537109817815727
    Line 303, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1500142276 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1500142276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 18.aes_core_fi.82573796798982311789133465680220134765643195179253941934714407911312735742258
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/18.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008057438 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008057438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.aes_core_fi.28079145968188936076480107003526800170628425145625833518804971507363941563719
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/24.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10013166272 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10013166272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_cipher_fi has 3 failures.
  - 95.aes_cipher_fi.23127525328501137347539172698514716116580321595930382771092704989974143713998
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/95.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10019491189 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10019491189 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 123.aes_cipher_fi.18279756510978181094907486161699628285315902152399596456467727858578819419550
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/123.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10002036736 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002036736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test aes_control_fi has 1 failures.
  - 0.aes_control_fi.19982048365065603090606996053734548195946256123538288463663301006069046124539
    Line 127, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/0.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.1262594519339322938682615223276230046045443963340089840867503921866939340638
    Line 608, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1187225603 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1187225603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_readability_vseq.sv:114) virtual_sequencer [aes_readability_vseq] ----| Data reg was did not clear |---- has 1 failures:
- Test aes_readability has 1 failures.
  - 10.aes_readability.10751070310384624075345829402254430721936705951129558751265902452032082526028
    Line 122, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/10.aes_readability/latest/run.log
```
  UVM_FATAL @   9325912 ps: (aes_readability_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_readability_vseq] ----| Data reg was did not clear |----
  UVM_INFO @   9325912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 20.aes_core_fi.81376460907259866931465762450914902576609587400311402299333671037233730160846
    Line 124, in log /workspaces/repo/scratch/os_regression_2024_08_24/aes_unmasked-sim-xcelium/20.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10018837373 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10018837373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```