AES/UNMASKED Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: `ed1c41cd0f`

Branch: os_regression_2024_08_31

Simulator: XCELIUM

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	105.664us	1	1	100.00
V1	smoke	aes_smoke	5.000s	182.257us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	68.605us	5	5	100.00
V1	csr_rw	aes_csr_rw	4.000s	100.341us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	13.000s	6.676ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	283.599us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	5.000s	76.419us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	4.000s	100.341us	20	20	100.00
		aes_csr_aliasing	6.000s	283.599us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	5.000s	182.257us	50	50	100.00
		aes_config_error	7.000s	177.758us	50	50	100.00
		aes_stress	6.000s	526.405us	50	50	100.00
V2	key_length	aes_smoke	5.000s	182.257us	50	50	100.00
		aes_config_error	7.000s	177.758us	50	50	100.00
		aes_stress	6.000s	526.405us	50	50	100.00
V2	back2back	aes_stress	6.000s	526.405us	50	50	100.00
		aes_b2b	11.000s	135.466us	50	50	100.00
V2	backpressure	aes_stress	6.000s	526.405us	50	50	100.00
V2	multi_message	aes_smoke	5.000s	182.257us	50	50	100.00
		aes_config_error	7.000s	177.758us	50	50	100.00
		aes_stress	6.000s	526.405us	50	50	100.00
		aes_alert_reset	6.000s	165.889us	50	50	100.00
V2	failure_test	aes_man_cfg_err	6.000s	96.692us	50	50	100.00
		aes_config_error	7.000s	177.758us	50	50	100.00
		aes_alert_reset	6.000s	165.889us	50	50	100.00
V2	trigger_clear_test	aes_clear	7.000s	200.846us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	8.000s	364.952us	1	1	100.00
V2	reset_recovery	aes_alert_reset	6.000s	165.889us	50	50	100.00
V2	stress	aes_stress	6.000s	526.405us	50	50	100.00
V2	sideload	aes_stress	6.000s	526.405us	50	50	100.00
		aes_sideload	6.000s	301.995us	50	50	100.00
V2	deinitialization	aes_deinit	6.000s	426.758us	50	50	100.00
V2	stress_all	aes_stress_all	33.000s	538.640us	10	10	100.00
V2	alert_test	aes_alert_test	5.000s	53.596us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	6.000s	805.630us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	6.000s	805.630us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	68.605us	5	5	100.00
		aes_csr_rw	4.000s	100.341us	20	20	100.00
		aes_csr_aliasing	6.000s	283.599us	5	5	100.00
		aes_same_csr_outstanding	4.000s	139.489us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	68.605us	5	5	100.00
		aes_csr_rw	4.000s	100.341us	20	20	100.00
		aes_csr_aliasing	6.000s	283.599us	5	5	100.00
		aes_same_csr_outstanding	4.000s	139.489us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	7.000s	156.172us	50	50	100.00
V2S	fault_inject	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_cipher_fi	59.000s	10.006ms	320	350	91.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	5.000s	150.768us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	5.000s	150.768us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	5.000s	150.768us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	5.000s	150.768us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	6.000s	920.624us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	11.000s	980.121us	5	5	100.00
		aes_tl_intg_err	5.000s	168.924us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	5.000s	168.924us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	6.000s	165.889us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	5.000s	150.768us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	5.000s	182.257us	50	50	100.00
		aes_stress	6.000s	526.405us	50	50	100.00
		aes_alert_reset	6.000s	165.889us	50	50	100.00
		aes_core_fi	1.800m	10.043ms	65	70	92.86
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	5.000s	150.768us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	5.000s	164.944us	50	50	100.00
		aes_stress	6.000s	526.405us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	6.000s	526.405us	50	50	100.00
		aes_sideload	6.000s	301.995us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	5.000s	164.944us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	5.000s	164.944us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	5.000s	164.944us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	5.000s	164.944us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	5.000s	164.944us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	6.000s	526.405us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	6.000s	526.405us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	9.000s	302.224us	49	50	98.00
V2S	sec_cm_main_fsm_redun	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_cipher_fi	59.000s	10.006ms	320	350	91.43
		aes_ctr_fi	5.000s	51.408us	50	50	100.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	9.000s	302.224us	49	50	98.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_cipher_fi	59.000s	10.006ms	320	350	91.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	59.000s	10.006ms	320	350	91.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	9.000s	302.224us	49	50	98.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_ctr_fi	5.000s	51.408us	50	50	100.00
V2S	sec_cm_ctrl_sparse	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_cipher_fi	59.000s	10.006ms	320	350	91.43
		aes_ctr_fi	5.000s	51.408us	50	50	100.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	6.000s	165.889us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_cipher_fi	59.000s	10.006ms	320	350	91.43
		aes_ctr_fi	5.000s	51.408us	50	50	100.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_cipher_fi	59.000s	10.006ms	320	350	91.43
		aes_ctr_fi	5.000s	51.408us	50	50	100.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_ctr_fi	5.000s	51.408us	50	50	100.00
V2S	sec_cm_data_reg_local_esc	aes_fi	9.000s	302.224us	49	50	98.00
		aes_control_fi	1.000m	10.006ms	274	300	91.33
		aes_cipher_fi	59.000s	10.006ms	320	350	91.43
V2S		TOTAL			923	985	93.71
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	26.000s	1.596ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1530	1602	95.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.24	97.57	94.52	98.81	93.74	97.72	93.33	98.66	96.21

Failure Buckets

Job timed out after * minutes has 40 failures:
- Test aes_cipher_fi has 21 failures.
  - 1.aes_cipher_fi.52576165816741212744052825445720604386827166476110519958244269884398073699352
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 11.aes_cipher_fi.112648583072271615275242528516562691016418344584108568885462732343144184537150
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/11.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 19 more failures.
- Test aes_control_fi has 19 failures.
  - 23.aes_control_fi.24427530652014990070542567922060652195768702546314791949474823617837010608796
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 27.aes_control_fi.77189357559651247544463597001752863012011137025523763392097444185272053493789
    Log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/27.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 17 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 10 failures:

Test aes_stress_all_with_rand_reset has 10 failures.

0.aes_stress_all_with_rand_reset.16061611684519426394037111950680422992197071068184903761206433619052197621272
Line 646, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 219521722 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 219521722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.1564774597058492166472293409138756720213881898283359599130620681099153273646
Line 611, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 719168960 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 719168960 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 6.aes_cipher_fi.15818116503865937905463369780876819428567091227980474378275430345102768670365
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10007265681 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007265681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.aes_cipher_fi.26484466829213103813366459375628593318579708535771635395047893787774025634966
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/23.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012239075 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012239075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 18.aes_control_fi.20203601257918024195403474825244357363274918702124618075415432304269453544042
    Line 138, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/18.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10003316434 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003316434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.aes_control_fi.62951991785198523235577014653543360805370031111000438484846159424647495822602
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/43.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004241467 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004241467 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 3 failures:
- Test aes_core_fi has 3 failures.
  - 1.aes_core_fi.109269487956365295908741939459723140653423542694931403578402882354904655608548
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/1.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10002216275 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10002216275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.aes_core_fi.16377670195036281468996927287722894544590422580598929311831153175695579536233
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003391044 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003391044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

31.aes_fi.75983113599481417863880000870849219708482791080746758892252925471871355561428
Line 460, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/31.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9103199 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9061532 PS)
  UVM_ERROR @   9103199 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   9103199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=6) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 42.aes_core_fi.45284411197253997772809016799861214839930329144014144634422405075576403240267
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/42.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10043419895 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xd0331184, Comparison=CompareOpEq, exp_data=0x0, call_count=6)
  UVM_INFO @ 10043419895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 44.aes_core_fi.39733356219076256318538053316217474583778524896837077761066295470672981848392
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_08_31/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10046817805 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10046817805 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```