AES/UNMASKED Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: XCELIUM

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	75.726us	1	1	100.00
V1	smoke	aes_smoke	1.433m	92.923us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	4.000s	63.852us	5	5	100.00
V1	csr_rw	aes_csr_rw	11.000s	93.757us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	14.000s	2.096ms	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	6.000s	622.406us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	11.000s	64.195us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	11.000s	93.757us	20	20	100.00
		aes_csr_aliasing	6.000s	622.406us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.433m	92.923us	50	50	100.00
		aes_config_error	1.633m	64.373us	50	50	100.00
		aes_stress	1.833m	86.844us	50	50	100.00
V2	key_length	aes_smoke	1.433m	92.923us	50	50	100.00
		aes_config_error	1.633m	64.373us	50	50	100.00
		aes_stress	1.833m	86.844us	50	50	100.00
V2	back2back	aes_stress	1.833m	86.844us	50	50	100.00
		aes_b2b	2.183m	709.012us	50	50	100.00
V2	backpressure	aes_stress	1.833m	86.844us	50	50	100.00
V2	multi_message	aes_smoke	1.433m	92.923us	50	50	100.00
		aes_config_error	1.633m	64.373us	50	50	100.00
		aes_stress	1.833m	86.844us	50	50	100.00
		aes_alert_reset	1.617m	75.439us	50	50	100.00
V2	failure_test	aes_man_cfg_err	2.083m	128.588us	50	50	100.00
		aes_config_error	1.633m	64.373us	50	50	100.00
		aes_alert_reset	1.617m	75.439us	50	50	100.00
V2	trigger_clear_test	aes_clear	2.083m	63.838us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	206.007us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.617m	75.439us	50	50	100.00
V2	stress	aes_stress	1.833m	86.844us	50	50	100.00
V2	sideload	aes_stress	1.833m	86.844us	50	50	100.00
		aes_sideload	2.117m	55.020us	50	50	100.00
V2	deinitialization	aes_deinit	1.617m	83.078us	50	50	100.00
V2	stress_all	aes_stress_all	2.183m	1.210ms	9	10	90.00
V2	alert_test	aes_alert_test	1.783m	53.138us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	11.000s	92.717us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	11.000s	92.717us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	4.000s	63.852us	5	5	100.00
		aes_csr_rw	11.000s	93.757us	20	20	100.00
		aes_csr_aliasing	6.000s	622.406us	5	5	100.00
		aes_same_csr_outstanding	11.000s	87.700us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	4.000s	63.852us	5	5	100.00
		aes_csr_rw	11.000s	93.757us	20	20	100.00
		aes_csr_aliasing	6.000s	622.406us	5	5	100.00
		aes_same_csr_outstanding	11.000s	87.700us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.383m	116.245us	50	50	100.00
V2S	fault_inject	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_cipher_fi	1.017m	54.354us	291	350	83.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	11.000s	132.331us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	11.000s	132.331us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	11.000s	132.331us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	11.000s	132.331us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	11.000s	62.663us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	39.000s	2.793ms	5	5	100.00
		aes_tl_intg_err	14.000s	781.093us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	14.000s	781.093us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.617m	75.439us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	11.000s	132.331us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.433m	92.923us	50	50	100.00
		aes_stress	1.833m	86.844us	50	50	100.00
		aes_alert_reset	1.617m	75.439us	50	50	100.00
		aes_core_fi	1.367m	62.731us	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	11.000s	132.331us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.683m	74.942us	50	50	100.00
		aes_stress	1.833m	86.844us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.833m	86.844us	50	50	100.00
		aes_sideload	2.117m	55.020us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.683m	74.942us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.683m	74.942us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.683m	74.942us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.683m	74.942us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.683m	74.942us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.833m	86.844us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.833m	86.844us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.900m	68.012us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_cipher_fi	1.017m	54.354us	291	350	83.14
		aes_ctr_fi	57.000s	62.911us	44	50	88.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.900m	68.012us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_cipher_fi	1.017m	54.354us	291	350	83.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	54.354us	291	350	83.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.900m	68.012us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_ctr_fi	57.000s	62.911us	44	50	88.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_cipher_fi	1.017m	54.354us	291	350	83.14
		aes_ctr_fi	57.000s	62.911us	44	50	88.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.617m	75.439us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_cipher_fi	1.017m	54.354us	291	350	83.14
		aes_ctr_fi	57.000s	62.911us	44	50	88.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_cipher_fi	1.017m	54.354us	291	350	83.14
		aes_ctr_fi	57.000s	62.911us	44	50	88.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_ctr_fi	57.000s	62.911us	44	50	88.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.900m	68.012us	50	50	100.00
		aes_control_fi	1.000m	46.307us	251	300	83.67
		aes_cipher_fi	1.017m	54.354us	291	350	83.14
V2S		TOTAL			868	985	88.12
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	2.283m	348.536us	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1474	1602	92.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.12	97.39	94.09	98.77	93.71	97.64	91.11	98.66	96.21

Failure Buckets

Job timed out after * minutes has 100 failures:
- Test aes_cipher_fi has 52 failures.
  - 3.aes_cipher_fi.28236674158502373117280838122839118835467396398429989269094616546459741283557
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/3.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 5.aes_cipher_fi.99707940091089734619161422334962605020240253002270153442555417756651418945905
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/5.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 50 more failures.
- Test aes_control_fi has 42 failures.
  - 4.aes_control_fi.107904515325483332553982449515179026398410832579414615901964441746279512165505
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/4.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 7.aes_control_fi.4478213639975231976959452884577546656322149205380658487694207209057031133824
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/7.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 40 more failures.
- Test aes_ctr_fi has 6 failures.
  - 6.aes_ctr_fi.96156435370117074049155040575946356733015865061769104029128940462442530250516
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/6.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 10.aes_ctr_fi.13387837217514512627662005855512890206626200524710710081623519089915268985852
    Log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/10.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 4 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 9 failures:

Test aes_stress_all_with_rand_reset has 9 failures.

0.aes_stress_all_with_rand_reset.9391315828535758956451758364732259483743525147123240896823803835235521097990
Line 522, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2366573270 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2366573270 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.30351148390253656072233611426506347157392434003898947245602766011372433325039
Line 1163, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 749225578 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 749225578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_control_fi has 7 failures.
  - 14.aes_control_fi.10874702776176282875088378917038390004370376971159807590122177229086406754004
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10006446764 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006446764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 15.aes_control_fi.56563973429398160767526191265978145375020982693045089757218901865114669608687
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10042292269 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10042292269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 63.aes_cipher_fi.17830076630259985022673335953754344413701376489381167424045462659908341111521
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/63.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10017589291 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10017589291 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 72.aes_cipher_fi.2701419125493178601071669914019509096064236740425424601583810658552713109249
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/72.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10005176326 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10005176326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 50.aes_core_fi.56724453124436083437915161573804455219299469243435962866641140369826904666349
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/50.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10033011939 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10033011939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 59.aes_core_fi.64642167044575249158415142978385967961463382157110212710210946595135369399180
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/59.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10003397958 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003397958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_stress_all has 1 failures.
  - 1.aes_stress_all.55784453231038785290902817864481092889182957121525113514350376936142517096426
    Line 10003, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/1.aes_stress_all/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 287709740 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 287689332 PS)
  UVM_ERROR @ 287709740 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @ 287709740 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.107430876802911540293080311894265153991217837049013956672755612153969348370888
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  26761573 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  26761573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 51.aes_core_fi.16487706933207432090943012474953568212936030982258930245969207259075376070933
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_03/aes_unmasked-sim-xcelium/51.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10012613143 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012613143 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```