AES/UNMASKED Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: XCELIUM

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	4.000s	62.986us	1	1	100.00
V1	smoke	aes_smoke	1.533m	60.426us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.150m	53.724us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.500m	100.912us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.367m	128.154us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	56.000s	173.296us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.533m	353.723us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.500m	100.912us	20	20	100.00
		aes_csr_aliasing	56.000s	173.296us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.533m	60.426us	50	50	100.00
		aes_config_error	1.550m	60.579us	50	50	100.00
		aes_stress	1.883m	148.626us	50	50	100.00
V2	key_length	aes_smoke	1.533m	60.426us	50	50	100.00
		aes_config_error	1.550m	60.579us	50	50	100.00
		aes_stress	1.883m	148.626us	50	50	100.00
V2	back2back	aes_stress	1.883m	148.626us	50	50	100.00
		aes_b2b	1.967m	111.933us	50	50	100.00
V2	backpressure	aes_stress	1.883m	148.626us	50	50	100.00
V2	multi_message	aes_smoke	1.533m	60.426us	50	50	100.00
		aes_config_error	1.550m	60.579us	50	50	100.00
		aes_stress	1.883m	148.626us	50	50	100.00
		aes_alert_reset	1.983m	75.516us	50	50	100.00
V2	failure_test	aes_man_cfg_err	1.883m	135.709us	50	50	100.00
		aes_config_error	1.550m	60.579us	50	50	100.00
		aes_alert_reset	1.983m	75.516us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.917m	83.787us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	7.000s	278.436us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.983m	75.516us	50	50	100.00
V2	stress	aes_stress	1.883m	148.626us	50	50	100.00
V2	sideload	aes_stress	1.883m	148.626us	50	50	100.00
		aes_sideload	1.733m	101.133us	50	50	100.00
V2	deinitialization	aes_deinit	1.467m	71.120us	50	50	100.00
V2	stress_all	aes_stress_all	36.000s	4.724ms	10	10	100.00
V2	alert_test	aes_alert_test	1.567m	105.419us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.383m	78.152us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.383m	78.152us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.150m	53.724us	5	5	100.00
		aes_csr_rw	1.500m	100.912us	20	20	100.00
		aes_csr_aliasing	56.000s	173.296us	5	5	100.00
		aes_same_csr_outstanding	1.200m	89.805us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.150m	53.724us	5	5	100.00
		aes_csr_rw	1.500m	100.912us	20	20	100.00
		aes_csr_aliasing	56.000s	173.296us	5	5	100.00
		aes_same_csr_outstanding	1.200m	89.805us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.900m	135.871us	50	50	100.00
V2S	fault_inject	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_cipher_fi	1.000m	73.971us	278	350	79.43
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.467m	109.291us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.467m	109.291us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.467m	109.291us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.467m	109.291us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.533m	104.934us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	10.000s	1.174ms	5	5	100.00
		aes_tl_intg_err	1.583m	1.329ms	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.583m	1.329ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.983m	75.516us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.467m	109.291us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.533m	60.426us	50	50	100.00
		aes_stress	1.883m	148.626us	50	50	100.00
		aes_alert_reset	1.983m	75.516us	50	50	100.00
		aes_core_fi	1.900m	81.861us	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.467m	109.291us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.483m	157.242us	50	50	100.00
		aes_stress	1.883m	148.626us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.883m	148.626us	50	50	100.00
		aes_sideload	1.733m	101.133us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.483m	157.242us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.483m	157.242us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.483m	157.242us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.483m	157.242us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.483m	157.242us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.883m	148.626us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.883m	148.626us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	1.917m	98.014us	47	50	94.00
V2S	sec_cm_main_fsm_redun	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_cipher_fi	1.000m	73.971us	278	350	79.43
		aes_ctr_fi	57.000s	106.833us	42	50	84.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	1.917m	98.014us	47	50	94.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_cipher_fi	1.000m	73.971us	278	350	79.43
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.000m	73.971us	278	350	79.43
V2S	sec_cm_ctr_fsm_sparse	aes_fi	1.917m	98.014us	47	50	94.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_ctr_fi	57.000s	106.833us	42	50	84.00
V2S	sec_cm_ctrl_sparse	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_cipher_fi	1.000m	73.971us	278	350	79.43
		aes_ctr_fi	57.000s	106.833us	42	50	84.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.983m	75.516us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_cipher_fi	1.000m	73.971us	278	350	79.43
		aes_ctr_fi	57.000s	106.833us	42	50	84.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_cipher_fi	1.000m	73.971us	278	350	79.43
		aes_ctr_fi	57.000s	106.833us	42	50	84.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_ctr_fi	57.000s	106.833us	42	50	84.00
V2S	sec_cm_data_reg_local_esc	aes_fi	1.917m	98.014us	47	50	94.00
		aes_control_fi	1.017m	66.126us	229	300	76.33
		aes_cipher_fi	1.000m	73.971us	278	350	79.43
V2S		TOTAL			828	985	84.06
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	19.000s	1.539ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1435	1602	89.58

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	6	54.55
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.19	97.54	94.43	98.79	93.57	97.64	91.85	98.66	96.41

Failure Buckets

Job timed out after * minutes has 133 failures:
- Test aes_control_fi has 60 failures.
  - 10.aes_control_fi.101874083909443368987526745698457618029271221091011429288315898826665641306504
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/10.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 17.aes_control_fi.113114259207365432279308108197152406211272637689755083367042514541535548591777
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/17.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 58 more failures.
- Test aes_cipher_fi has 65 failures.
  - 10.aes_cipher_fi.83829683195521753254315279675454220054831401919704426151942065117018303484624
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 24.aes_cipher_fi.52995028018720921272991715215526353875820006976177746422333037919746650464694
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/24.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 63 more failures.
- Test aes_ctr_fi has 8 failures.
  - 11.aes_ctr_fi.72361447001046150257765838529441163989675786536586075164211775027383218356199
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/11.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 24.aes_ctr_fi.14620555169210348627704084756861192065779419668519811668901749917929157649457
    Log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/24.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 6 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 11 failures:
- Test aes_control_fi has 11 failures.
  - 23.aes_control_fi.60831484526998258301877187369127107903532311995515100311601023464142379964778
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/23.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10026498378 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10026498378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 42.aes_control_fi.55731677959698799483703508946227236969374183713881768005581646519859972272992
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/42.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10110040207 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10110040207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 7 failures:
- Test aes_cipher_fi has 7 failures.
  - 1.aes_cipher_fi.7715974342016743309557017932738537568445331549959253428659950673534801714535
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/1.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10016299356 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016299356 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_cipher_fi.18509987492140275440944318555400369435936371636655093421965659557464666106116
    Line 135, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/9.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10003404448 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10003404448 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 6 failures:

Test aes_stress_all_with_rand_reset has 6 failures.

0.aes_stress_all_with_rand_reset.112014463515548202465788339733898453720793930903751836329487814314481403701242
Line 544, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 740202575 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 740202575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aes_stress_all_with_rand_reset.42861695597966722878848187859995125719399360799122734170778922206140866184251
Line 356, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 247712094 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 247712094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.9848095564795979016964801196249611130422367576340355017628934213120664780176
    Line 315, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  77908995 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  77908995 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.aes_stress_all_with_rand_reset.73891233568380764990985493822114424664442197921480961211751129047014786984879
    Line 211, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/7.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 215197327 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 215197327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_core_fi has 2 failures.
  - 25.aes_core_fi.83194213114158234236335645208232369871630527845404392572539552422599555260940
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/25.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10022586518 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10022586518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 44.aes_core_fi.62646897603578648055357466596315396828182640139281254640874055033220345092062
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/44.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10187853439 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10187853439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,993): Assertion AesSecCmDataRegLocalEscIv has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

0.aes_fi.707898914344510345961269349312926890769147140311109945130875021875971713972
Line 3195, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/0.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 49746208 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 49690652 PS)
  UVM_ERROR @  49746208 ps: (aes_core.sv:993) [ASSERT FAILED] AesSecCmDataRegLocalEscIv
  UVM_INFO @  49746208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 5.aes_stress_all_with_rand_reset.50626950165956304302251190842270696034147191834862851757873753230049274238925
    Line 143, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 105182739 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 105182739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:557) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 6.aes_stress_all_with_rand_reset.101182362376154874682233897381812110840460517196339384974910340042600788890448
    Line 272, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/6.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 746426577 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 746426577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 12.aes_core_fi.44164893433658672700058809218796979781683531186177697073151453292889164463131
    Line 131, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/12.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10016135037 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10016135037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_fi_vseq.sv:69) virtual_sequencer [aes_fi_vseq] Was Able to finish without clearing reset has 1 failures:
- Test aes_fi has 1 failures.
  - 44.aes_fi.94111663021180318876364174274255202663112001204010603854551043594875808246660
    Line 4071, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/44.aes_fi/latest/run.log
```
  UVM_FATAL @ 181820399 ps: (aes_fi_vseq.sv:69) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.aes_fi_vseq] Was Able to finish without clearing reset
  UVM_INFO @ 181820399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:

Test aes_fi has 1 failures.

46.aes_fi.34949499569918889020387436909088063942287608674173880687689520017156954007217
Line 1091, in log /workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/46.aes_fi/latest/run.log

  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9241225 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9220392 PS)
        ($past(iv_q) != $past(state_done_transposed, 2) ^ $past(data_in_prev_q, 2)))
                                                                                   |
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_08/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,993): (time 9241225 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscIv has failed (2 cycles, starting 9220392 PS)
  UVM_ERROR @   9241225 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut