AES/UNMASKED Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: `25b1acbf68`

Branch: os_regression_2024_09_10

Simulator: XCELIUM

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	3.000s	59.984us	1	1	100.00
V1	smoke	aes_smoke	1.950m	90.165us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.017m	51.749us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.850m	140.585us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	1.033m	190.847us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	34.000s	1.262ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.950m	120.984us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.850m	140.585us	20	20	100.00
		aes_csr_aliasing	34.000s	1.262ms	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.950m	90.165us	50	50	100.00
		aes_config_error	1.550m	140.969us	50	50	100.00
		aes_stress	2.017m	62.219us	50	50	100.00
V2	key_length	aes_smoke	1.950m	90.165us	50	50	100.00
		aes_config_error	1.550m	140.969us	50	50	100.00
		aes_stress	2.017m	62.219us	50	50	100.00
V2	back2back	aes_stress	2.017m	62.219us	50	50	100.00
		aes_b2b	1.683m	133.422us	50	50	100.00
V2	backpressure	aes_stress	2.017m	62.219us	50	50	100.00
V2	multi_message	aes_smoke	1.950m	90.165us	50	50	100.00
		aes_config_error	1.550m	140.969us	50	50	100.00
		aes_stress	2.017m	62.219us	50	50	100.00
		aes_alert_reset	2.133m	59.407us	50	50	100.00
V2	failure_test	aes_man_cfg_err	2.067m	98.339us	50	50	100.00
		aes_config_error	1.550m	140.969us	50	50	100.00
		aes_alert_reset	2.133m	59.407us	50	50	100.00
V2	trigger_clear_test	aes_clear	1.533m	213.530us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	13.000s	110.412us	1	1	100.00
V2	reset_recovery	aes_alert_reset	2.133m	59.407us	50	50	100.00
V2	stress	aes_stress	2.017m	62.219us	50	50	100.00
V2	sideload	aes_stress	2.017m	62.219us	50	50	100.00
		aes_sideload	3.167m	100.603us	50	50	100.00
V2	deinitialization	aes_deinit	1.700m	96.814us	50	50	100.00
V2	stress_all	aes_stress_all	1.633m	363.851us	10	10	100.00
V2	alert_test	aes_alert_test	1.883m	51.058us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.833m	206.036us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.833m	206.036us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.017m	51.749us	5	5	100.00
		aes_csr_rw	1.850m	140.585us	20	20	100.00
		aes_csr_aliasing	34.000s	1.262ms	5	5	100.00
		aes_same_csr_outstanding	1.933m	57.020us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.017m	51.749us	5	5	100.00
		aes_csr_rw	1.850m	140.585us	20	20	100.00
		aes_csr_aliasing	34.000s	1.262ms	5	5	100.00
		aes_same_csr_outstanding	1.933m	57.020us	20	20	100.00
V2		TOTAL			501	501	100.00
V2S	reseeding	aes_reseed	1.900m	87.600us	50	50	100.00
V2S	fault_inject	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_cipher_fi	1.017m	50.092us	280	350	80.00
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.517m	65.910us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.517m	65.910us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.517m	65.910us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.517m	65.910us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.850m	112.501us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.450m	672.180us	5	5	100.00
		aes_tl_intg_err	1.867m	562.940us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	1.867m	562.940us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	2.133m	59.407us	50	50	100.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.517m	65.910us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.950m	90.165us	50	50	100.00
		aes_stress	2.017m	62.219us	50	50	100.00
		aes_alert_reset	2.133m	59.407us	50	50	100.00
		aes_core_fi	1.850m	10.051ms	67	70	95.71
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.517m	65.910us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	2.050m	64.956us	50	50	100.00
		aes_stress	2.017m	62.219us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	2.017m	62.219us	50	50	100.00
		aes_sideload	3.167m	100.603us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	2.050m	64.956us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	2.050m	64.956us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	2.050m	64.956us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	2.050m	64.956us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	2.050m	64.956us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	2.017m	62.219us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	2.017m	62.219us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.533m	141.765us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_cipher_fi	1.017m	50.092us	280	350	80.00
		aes_ctr_fi	52.000s	55.913us	37	50	74.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.533m	141.765us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_cipher_fi	1.017m	50.092us	280	350	80.00
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	50.092us	280	350	80.00
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.533m	141.765us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_ctr_fi	52.000s	55.913us	37	50	74.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_cipher_fi	1.017m	50.092us	280	350	80.00
		aes_ctr_fi	52.000s	55.913us	37	50	74.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	2.133m	59.407us	50	50	100.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_cipher_fi	1.017m	50.092us	280	350	80.00
		aes_ctr_fi	52.000s	55.913us	37	50	74.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_cipher_fi	1.017m	50.092us	280	350	80.00
		aes_ctr_fi	52.000s	55.913us	37	50	74.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_ctr_fi	52.000s	55.913us	37	50	74.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.533m	141.765us	50	50	100.00
		aes_control_fi	1.017m	64.747us	235	300	78.33
		aes_cipher_fi	1.017m	50.092us	280	350	80.00
V2S		TOTAL			834	985	84.67
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.900m	4.272ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1441	1602	89.95

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	13	100.00
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.21	97.52	94.39	98.81	93.65	97.72	93.33	98.66	96.21

Failure Buckets

Job timed out after * minutes has 137 failures:
- Test aes_cipher_fi has 61 failures.
  - 6.aes_cipher_fi.23561498567896676254564198663468450637779077701114183071878057590324774710923
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_cipher_fi.77889117411418357778911556646382224534072370931609077116544895204368110562132
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/14.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 59 more failures.
- Test aes_ctr_fi has 13 failures.
  - 6.aes_ctr_fi.28156889413081980981077047410618341247586709267100125383571833380386277115284
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/6.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 7.aes_ctr_fi.68198313780540993744972137978446398172523271667067812952153920907194402462695
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/7.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 11 more failures.
- Test aes_control_fi has 63 failures.
  - 14.aes_control_fi.52181714814381121140287087557858874857787954666224746372286956766652929145908
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/14.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 15.aes_control_fi.55748713530751603505509898345910526554811560856476645281458197058717070770980
    Log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/15.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 61 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 9 failures:
- Test aes_cipher_fi has 9 failures.
  - 179.aes_cipher_fi.2990816672293166828061429646257184510251828563877878269821130951658301734447
    Line 137, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/179.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10010322068 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10010322068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 262.aes_cipher_fi.36465943682280297368559577141294140881262002699590416758851179563780620608459
    Line 136, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/262.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10006897323 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006897323 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 7 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 4 failures:

Test aes_stress_all_with_rand_reset has 4 failures.

0.aes_stress_all_with_rand_reset.104649673974032827734694402462889409471155818604511317707480448086514974545325
Line 304, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2222546168 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 2222546168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.65292938931422783319254879838483923297634578193327762346376103953345179646258
Line 717, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1536005137 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 1536005137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 1.aes_stress_all_with_rand_reset.89248932569949643025967177481966280385956136440395658430632209930749606711337
    Line 150, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  29657382 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  29657382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 5.aes_stress_all_with_rand_reset.51020189858639415682246720937677758802977555198513539858518484574067594896753
    Line 430, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/5.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1909319936 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1909319936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 2.aes_stress_all_with_rand_reset.42016565898928158048597619455462479236051594863532606230622318371534832575544
    Line 165, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  75999080 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  75999080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 8.aes_stress_all_with_rand_reset.98488439184056844977783308448479142720808409836732434100054586540680372365049
    Line 829, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 7424333780 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 7424333780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:557) [aes_alert_reset_vseq] Check failed * == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (* [*] vs * [*]) Alert fatal_fault fired unexpectedly! has 2 failures:
- Test aes_stress_all_with_rand_reset has 2 failures.
  - 4.aes_stress_all_with_rand_reset.115202197424507107925701154253979941806900165664162036095372316103548639546344
    Line 360, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/4.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 4271585043 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @ 4271585043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 9.aes_stress_all_with_rand_reset.79193237212832347594827235965112335828524503653360546569522378961116422572324
    Line 125, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/9.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  36523925 ps: (cip_base_vseq.sv:557) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed 0 == cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() (0 [0x0] vs 1 [0x1]) Alert fatal_fault fired unexpectedly!
  UVM_INFO @  36523925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 2 failures:
- Test aes_control_fi has 2 failures.
  - 243.aes_control_fi.33784878560641465572684411017805228992093521474418209670329418036186746844511
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/243.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10037545494 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10037545494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 260.aes_control_fi.57304565028746372528887055110914276187133560019497183592283257731706523496179
    Line 133, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/260.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10015780940 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015780940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 39.aes_core_fi.91168533742991216512098579006387104378309667985474056534642863898103805403870
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/39.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10014907113 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10014907113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 64.aes_core_fi.45156731970387358327306734314063013567986863243324130645418656072868601147039
    Line 128, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/64.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10050911470 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0xbc156184, Comparison=CompareOpEq, exp_data=0x0, call_count=8)
  UVM_INFO @ 10050911470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 68.aes_core_fi.7642786263900298988473022961498903035296401145343315345385435404726650832407
    Line 126, in log /workspaces/repo/scratch/os_regression_2024_09_10/aes_unmasked-sim-xcelium/68.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10007920954 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10007920954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```