AES/UNMASKED Simulation Results

Wednesday September 18 2024 00:48:27 UTC

GitHub Revision: `7e34e67ade`

Branch: os_regression_2024_09_17

Simulator: XCELIUM

Build randomization enabled with --build-seed 4190660412037082522497784440658734031572790705268868319466386425736861254975

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	wake_up	aes_wake_up	42.000s	76.583us	1	1	100.00
V1	smoke	aes_smoke	1.567m	88.062us	50	50	100.00
V1	csr_hw_reset	aes_csr_hw_reset	1.483m	81.676us	5	5	100.00
V1	csr_rw	aes_csr_rw	1.500m	61.799us	20	20	100.00
V1	csr_bit_bash	aes_csr_bit_bash	2.083m	447.030us	5	5	100.00
V1	csr_aliasing	aes_csr_aliasing	2.050m	83.746us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aes_csr_mem_rw_with_rand_reset	1.567m	96.722us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aes_csr_rw	1.500m	61.799us	20	20	100.00
		aes_csr_aliasing	2.050m	83.746us	5	5	100.00
V1		TOTAL			106	106	100.00
V2	algorithm	aes_smoke	1.567m	88.062us	50	50	100.00
		aes_config_error	1.733m	214.709us	50	50	100.00
		aes_stress	1.883m	586.609us	50	50	100.00
V2	key_length	aes_smoke	1.567m	88.062us	50	50	100.00
		aes_config_error	1.733m	214.709us	50	50	100.00
		aes_stress	1.883m	586.609us	50	50	100.00
V2	back2back	aes_stress	1.883m	586.609us	50	50	100.00
		aes_b2b	1.750m	149.320us	50	50	100.00
V2	backpressure	aes_stress	1.883m	586.609us	50	50	100.00
V2	multi_message	aes_smoke	1.567m	88.062us	50	50	100.00
		aes_config_error	1.733m	214.709us	50	50	100.00
		aes_stress	1.883m	586.609us	50	50	100.00
		aes_alert_reset	1.933m	325.213us	49	50	98.00
V2	failure_test	aes_man_cfg_err	1.850m	126.419us	50	50	100.00
		aes_config_error	1.733m	214.709us	50	50	100.00
		aes_alert_reset	1.933m	325.213us	49	50	98.00
V2	trigger_clear_test	aes_clear	2.250m	298.255us	50	50	100.00
V2	nist_test_vectors	aes_nist_vectors	45.000s	182.510us	1	1	100.00
V2	reset_recovery	aes_alert_reset	1.933m	325.213us	49	50	98.00
V2	stress	aes_stress	1.883m	586.609us	50	50	100.00
V2	sideload	aes_stress	1.883m	586.609us	50	50	100.00
		aes_sideload	1.883m	54.979us	50	50	100.00
V2	deinitialization	aes_deinit	1.867m	73.975us	50	50	100.00
V2	stress_all	aes_stress_all	1.550m	1.625ms	10	10	100.00
V2	alert_test	aes_alert_test	1.867m	76.489us	50	50	100.00
V2	tl_d_oob_addr_access	aes_tl_errors	1.567m	80.842us	20	20	100.00
V2	tl_d_illegal_access	aes_tl_errors	1.567m	80.842us	20	20	100.00
V2	tl_d_outstanding_access	aes_csr_hw_reset	1.483m	81.676us	5	5	100.00
		aes_csr_rw	1.500m	61.799us	20	20	100.00
		aes_csr_aliasing	2.050m	83.746us	5	5	100.00
		aes_same_csr_outstanding	2.050m	349.927us	20	20	100.00
V2	tl_d_partial_access	aes_csr_hw_reset	1.483m	81.676us	5	5	100.00
		aes_csr_rw	1.500m	61.799us	20	20	100.00
		aes_csr_aliasing	2.050m	83.746us	5	5	100.00
		aes_same_csr_outstanding	2.050m	349.927us	20	20	100.00
V2		TOTAL			500	501	99.80
V2S	reseeding	aes_reseed	1.883m	63.477us	50	50	100.00
V2S	fault_inject	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_cipher_fi	1.017m	56.427us	291	350	83.14
V2S	shadow_reg_update_error	aes_shadow_reg_errors	1.550m	162.865us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	aes_shadow_reg_errors	1.550m	162.865us	20	20	100.00
V2S	shadow_reg_storage_error	aes_shadow_reg_errors	1.550m	162.865us	20	20	100.00
V2S	shadowed_reset_glitch	aes_shadow_reg_errors	1.550m	162.865us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	aes_shadow_reg_errors_with_csr_rw	1.700m	73.889us	20	20	100.00
V2S	tl_intg_err	aes_sec_cm	1.000m	1.682ms	5	5	100.00
		aes_tl_intg_err	2.033m	300.750us	20	20	100.00
V2S	sec_cm_bus_integrity	aes_tl_intg_err	2.033m	300.750us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	aes_alert_reset	1.933m	325.213us	49	50	98.00
V2S	sec_cm_main_config_shadow	aes_shadow_reg_errors	1.550m	162.865us	20	20	100.00
V2S	sec_cm_main_config_sparse	aes_smoke	1.567m	88.062us	50	50	100.00
		aes_stress	1.883m	586.609us	50	50	100.00
		aes_alert_reset	1.933m	325.213us	49	50	98.00
		aes_core_fi	1.917m	56.308us	63	70	90.00
V2S	sec_cm_aux_config_shadow	aes_shadow_reg_errors	1.550m	162.865us	20	20	100.00
V2S	sec_cm_aux_config_regwen	aes_readability	1.883m	67.456us	50	50	100.00
		aes_stress	1.883m	586.609us	50	50	100.00
V2S	sec_cm_key_sideload	aes_stress	1.883m	586.609us	50	50	100.00
		aes_sideload	1.883m	54.979us	50	50	100.00
V2S	sec_cm_key_sw_unreadable	aes_readability	1.883m	67.456us	50	50	100.00
V2S	sec_cm_data_reg_sw_unreadable	aes_readability	1.883m	67.456us	50	50	100.00
V2S	sec_cm_key_sec_wipe	aes_readability	1.883m	67.456us	50	50	100.00
V2S	sec_cm_iv_config_sec_wipe	aes_readability	1.883m	67.456us	50	50	100.00
V2S	sec_cm_data_reg_sec_wipe	aes_readability	1.883m	67.456us	50	50	100.00
V2S	sec_cm_data_reg_key_sca	aes_stress	1.883m	586.609us	50	50	100.00
V2S	sec_cm_key_masking	aes_stress	1.883m	586.609us	50	50	100.00
V2S	sec_cm_main_fsm_sparse	aes_fi	2.183m	91.707us	50	50	100.00
V2S	sec_cm_main_fsm_redun	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_cipher_fi	1.017m	56.427us	291	350	83.14
		aes_ctr_fi	59.000s	52.475us	43	50	86.00
V2S	sec_cm_cipher_fsm_sparse	aes_fi	2.183m	91.707us	50	50	100.00
V2S	sec_cm_cipher_fsm_redun	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_cipher_fi	1.017m	56.427us	291	350	83.14
V2S	sec_cm_cipher_ctr_redun	aes_cipher_fi	1.017m	56.427us	291	350	83.14
V2S	sec_cm_ctr_fsm_sparse	aes_fi	2.183m	91.707us	50	50	100.00
V2S	sec_cm_ctr_fsm_redun	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_ctr_fi	59.000s	52.475us	43	50	86.00
V2S	sec_cm_ctrl_sparse	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_cipher_fi	1.017m	56.427us	291	350	83.14
		aes_ctr_fi	59.000s	52.475us	43	50	86.00
V2S	sec_cm_main_fsm_global_esc	aes_alert_reset	1.933m	325.213us	49	50	98.00
V2S	sec_cm_main_fsm_local_esc	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_cipher_fi	1.017m	56.427us	291	350	83.14
		aes_ctr_fi	59.000s	52.475us	43	50	86.00
V2S	sec_cm_cipher_fsm_local_esc	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_cipher_fi	1.017m	56.427us	291	350	83.14
		aes_ctr_fi	59.000s	52.475us	43	50	86.00
V2S	sec_cm_ctr_fsm_local_esc	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_ctr_fi	59.000s	52.475us	43	50	86.00
V2S	sec_cm_data_reg_local_esc	aes_fi	2.183m	91.707us	50	50	100.00
		aes_control_fi	1.000m	56.628us	244	300	81.33
		aes_cipher_fi	1.017m	56.427us	291	350	83.14
V2S		TOTAL			856	985	86.90
V3	stress_all_with_rand_reset	aes_stress_all_with_rand_reset	1.667m	1.969ms	0	10	0.00
V3		TOTAL			0	10	0.00
		TOTAL			1462	1602	91.26

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	13	13	12	92.31
V2S	11	11	7	63.64
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
97.16	97.46	94.26	98.77	93.71	97.64	91.11	98.85	96.21

Failure Buckets

Job timed out after * minutes has 113 failures:
- Test aes_control_fi has 51 failures.
  - 1.aes_control_fi.112438806250138713099242714194811643566991126741122097422184207594234467732194
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/1.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 2.aes_control_fi.64541775613310208048395987595931952683898973643025253061582632022168234372596
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/2.aes_control_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 49 more failures.
- Test aes_ctr_fi has 7 failures.
  - 3.aes_ctr_fi.105367584457174318145273741434238081183850648657135627266801460183433666748463
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/3.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 14.aes_ctr_fi.111205202672278906910829133798308171057180875079027956754478838742576301816070
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/14.aes_ctr_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 5 more failures.
- Test aes_cipher_fi has 55 failures.
  - 6.aes_cipher_fi.76280416029116592238789622196578518280384295129041770834821286575848859536814
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/6.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - 10.aes_cipher_fi.12703947257969933605171739316251151841860601222925124090640088725549070483788
    Log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/10.aes_cipher_fi/latest/run.log
```
  Job timed out after 1 minutes
```
  - ... and 53 more failures.

UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 7 failures:

Test aes_stress_all_with_rand_reset has 7 failures.

0.aes_stress_all_with_rand_reset.4391050252823920208520913136570804669719623203749472950540844232641606897094
Line 183, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 286238958 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_stress_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @ 286238958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.aes_stress_all_with_rand_reset.44446549071512593255615645632051621851643139217167096672364025098205351404544
Line 161, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/3.aes_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  36513033 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.keymgr_sideload_agent.sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.keymgr_sideload_agent.sequencer' for sequence 'uvm_test_top.env.virtual_sequencer.aes_reseed_vseq.sideload_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  36513033 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

UVM_FATAL (aes_core_fi_vseq.sv:66) [aes_core_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_core_fi has 5 failures.
  - 22.aes_core_fi.112230160032099665655318090067608273166045395753096540489271689308910796190700
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/22.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10015451964 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10015451964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 36.aes_core_fi.2773012571935579818032898611566943779813503606820927440053744243013811597253
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/36.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10006047169 ps: (aes_core_fi_vseq.sv:66) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10006047169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! has 5 failures:
- Test aes_control_fi has 5 failures.
  - 136.aes_control_fi.85563521468264199322999635005853812954624312635279421200112582394295247603814
    Line 139, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/136.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10009985618 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10009985618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 178.aes_control_fi.81888134767801880083184090094317425597562941481083751005894202669349984400106
    Line 144, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/178.aes_control_fi/latest/run.log
```
  UVM_FATAL @ 10004247103 ps: (aes_control_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_control_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10004247103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred! has 4 failures:
- Test aes_cipher_fi has 4 failures.
  - 44.aes_cipher_fi.22698942254296972730335587664425478139006961477824292724257749260349293363612
    Line 134, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/44.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10011171312 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10011171312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 210.aes_cipher_fi.55029824681367025051593721749901220118333532017114482216510757192781441105232
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/210.aes_cipher_fi/latest/run.log
```
  UVM_FATAL @ 10012793480 ps: (aes_cipher_fi_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.aes_cipher_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10012793480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (aes_base_vseq.sv:74) [aes_reseed_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 1.aes_stress_all_with_rand_reset.14257105867980898441631500928517406448045353307154617194496206272788568582814
    Line 614, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/1.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 1968691090 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_reseed_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 1968691090 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 2.aes_stress_all_with_rand_reset.84855187581038300358027031264659246298119434984475864629312734787905397292001
    Line 526, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/2.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 4055676979 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_stress_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @ 4055676979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_base_vseq.sv:74) [aes_alert_reset_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed) has 1 failures:
- Test aes_stress_all_with_rand_reset has 1 failures.
  - 8.aes_stress_all_with_rand_reset.71108956770308211831081528473490120944487365342743178791803833274953923914276
    Line 158, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/8.aes_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @  17330218 ps: (aes_base_vseq.sv:74) [uvm_test_top.env.virtual_sequencer.aes_alert_reset_vseq] Check failed (aes_ctrl_aux[0] == cfg.do_reseed)
  UVM_INFO @  17330218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_*_*_*/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_*/rtl/aes_core.sv,987): Assertion AesSecCmDataRegLocalEscDataOut has failed (* cycles, starting * PS) has 1 failures:
- Test aes_alert_reset has 1 failures.
  - 15.aes_alert_reset.104444031312608413555313168958154086244184835358461667211349946617072509988477
    Line 3274, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/15.aes_alert_reset/latest/run.log
```
  xmsim: *E,ASRTST (/workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/default/src/lowrisc_ip_aes_1.0/rtl/aes_core.sv,987): (time 9819700 PS) Assertion tb.dut.u_aes_core.AesSecCmDataRegLocalEscDataOut has failed (2 cycles, starting 9809700 PS)
  UVM_ERROR @   9819700 ps: (aes_core.sv:987) [ASSERT FAILED] AesSecCmDataRegLocalEscDataOut
  UVM_INFO @   9819700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=7) has 1 failures:
- Test aes_core_fi has 1 failures.
  - 28.aes_core_fi.113263622719690556819184990594930443241281793357204042047624285476769916365956
    Line 130, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/28.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10051094692 ps: (csr_utils_pkg.sv:587) [csr_utils::csr_spinwait] timeout aes_reg_block.status.idle (addr=0x68568484, Comparison=CompareOpEq, exp_data=0x0, call_count=7)
  UVM_INFO @ 10051094692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (aes_core_fi_vseq.sv:89) [aes_core_fi_vseq] wait timeout occurred! has 1 failures:
- Test aes_core_fi has 1 failures.
  - 35.aes_core_fi.254486442825045716931281919391580094190060302207552657792141199081387980103
    Line 129, in log /workspaces/repo/scratch/os_regression_2024_09_17/aes_unmasked-sim-xcelium/35.aes_core_fi/latest/run.log
```
  UVM_FATAL @ 10008251243 ps: (aes_core_fi_vseq.sv:89) [uvm_test_top.env.virtual_sequencer.aes_core_fi_vseq] wait timeout occurred!
  UVM_INFO @ 10008251243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```